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mb/google/brask/var/bujia: Configure Serial IO UARTs Mode

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This patch configures Serial IO UARTs mode as below.

UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design.

BUG=b:338917836
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot

Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Shon Wang 2024-06-25 16:01:00 +08:00 committed by Felix Held
parent d5658fd7c0
commit 2ebfb79d33
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/brya/variants/bujia/overridetree.cb
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@ -46,6 +46,12 @@ chip soc/intel/alderlake
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}" }"
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoPci,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
register "ddi_ports_config" = "{ register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD, [DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,