soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info
Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq' to better describe what it's doing. This struct element contains the number of the northbridge IOAPIC IRQ input the bridge IRQ is connected to signal power management or error reporting IRQs. Right now, coreboot doesn't put this information into the ACPI bytecode. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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@@ -57,7 +57,7 @@ struct pci_routing_info {
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uint8_t devfn;
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uint8_t devfn;
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uint8_t group;
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uint8_t group;
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uint8_t swizzle;
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uint8_t swizzle;
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uint8_t irq;
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uint8_t bridge_irq; /* also called 'map' */
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} __packed;
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} __packed;
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void populate_pirq_data(void);
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void populate_pirq_data(void);
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@@ -34,9 +34,9 @@ const struct pci_routing_info *get_pci_routing_table(size_t *entries)
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routing_table_entries = routing_hob->num_of_entries;
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routing_table_entries = routing_hob->num_of_entries;
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for (size_t i = 0; i < routing_table_entries; ++i) {
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for (size_t i = 0; i < routing_table_entries; ++i) {
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printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n",
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printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, bridge irq: %u\n",
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PCI_SLOT(routing_table[i].devfn), PCI_FUNC(routing_table[i].devfn),
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PCI_SLOT(routing_table[i].devfn), PCI_FUNC(routing_table[i].devfn),
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routing_table[i].group, routing_table[i].swizzle, routing_table[i].irq);
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routing_table[i].group, routing_table[i].swizzle, routing_table[i].bridge_irq);
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}
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}
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*entries = routing_table_entries;
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*entries = routing_table_entries;
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