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soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info

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Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq'
to better describe what it's doing. This struct element contains the
number of the northbridge IOAPIC IRQ input the bridge IRQ is connected
to signal power management or error reporting IRQs. Right now, coreboot
doesn't put this information into the ACPI bytecode.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held
2024-04-19 18:35:15 +02:00
parent 6ad7513e03
commit 2ec63b54d8
2 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
View File

@@ -57,7 +57,7 @@ struct pci_routing_info {
uint8_t devfn;
uint8_t group;
uint8_t swizzle;
uint8_t irq;
uint8_t bridge_irq; /* also called 'map' */
} __packed;
void populate_pirq_data(void);

4
src/soc/amd/common/fsp/pci/pci_routing_info.c
View File

@@ -34,9 +34,9 @@ const struct pci_routing_info *get_pci_routing_table(size_t *entries)
routing_table_entries = routing_hob->num_of_entries;
for (size_t i = 0; i < routing_table_entries; ++i) {
printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n",
printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, bridge irq: %u\n",
PCI_SLOT(routing_table[i].devfn), PCI_FUNC(routing_table[i].devfn),
routing_table[i].group, routing_table[i].swizzle, routing_table[i].irq);
routing_table[i].group, routing_table[i].swizzle, routing_table[i].bridge_irq);
}
*entries = routing_table_entries;