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mb/google/brox: Enable SAGv

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Enable SaGv support for brox

BUG=None
BRANCH=None
TEST=Boot brox with SAGv enabled and verify in fsp debug logs

Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ashish Kumar Mishra
2024-03-28 14:49:32 +05:30
committed by Felix Held
parent 055c6d5c34
commit 2ed80b16b3
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
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@@ -11,6 +11,9 @@ chip soc/intel/alderlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable SAGv
register "sagv" = "SaGv_Enabled"
# S0ix enable
register "s0ix_enable" = "1"