soc/pci_devs.h: Use consistent naming in soc/pci_devs.h
This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
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Martin Roth
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fc4c7d8320
commit
2ee54db246
@ -54,59 +54,59 @@ static const char *soc_acpi_name(struct device *dev)
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switch (dev->path.pci.devfn) {
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/* DSDT: acpi/northbridge.asl */
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case NB_DEVFN:
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case SA_DEVFN_ROOT:
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return "MCHC";
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/* DSDT: acpi/lpc.asl */
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case LPC_DEVFN:
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case PCH_DEVFN_LPC:
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return "LPCB";
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/* DSDT: acpi/xhci.asl */
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case XHCI_DEVFN:
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case PCH_DEVFN_XHCI:
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return "XHCI";
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/* DSDT: acpi/pch_hda.asl */
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case HDA_DEVFN:
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case PCH_DEVFN_HDA:
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return "HDAS";
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/* DSDT: acpi/lpss.asl */
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case LPSS_DEVFN_UART0:
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case PCH_DEVFN_UART0:
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return "URT1";
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case LPSS_DEVFN_UART1:
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case PCH_DEVFN_UART1:
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return "URT2";
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case LPSS_DEVFN_UART2:
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case PCH_DEVFN_UART2:
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return "URT3";
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case LPSS_DEVFN_UART3:
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case PCH_DEVFN_UART3:
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return "URT4";
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case LPSS_DEVFN_SPI0:
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case PCH_DEVFN_SPI0:
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return "SPI1";
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case LPSS_DEVFN_SPI1:
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case PCH_DEVFN_SPI1:
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return "SPI2";
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case LPSS_DEVFN_SPI2:
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case PCH_DEVFN_SPI2:
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return "SPI3";
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case LPSS_DEVFN_PWM:
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case PCH_DEVFN_PWM:
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return "PWM";
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case LPSS_DEVFN_I2C0:
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case PCH_DEVFN_I2C0:
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return "I2C0";
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case LPSS_DEVFN_I2C1:
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case PCH_DEVFN_I2C1:
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return "I2C1";
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case LPSS_DEVFN_I2C2:
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case PCH_DEVFN_I2C2:
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return "I2C2";
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case LPSS_DEVFN_I2C3:
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case PCH_DEVFN_I2C3:
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return "I2C3";
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case LPSS_DEVFN_I2C4:
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case PCH_DEVFN_I2C4:
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return "I2C4";
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case LPSS_DEVFN_I2C5:
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case PCH_DEVFN_I2C5:
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return "I2C5";
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case LPSS_DEVFN_I2C6:
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case PCH_DEVFN_I2C6:
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return "I2C6";
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case LPSS_DEVFN_I2C7:
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case PCH_DEVFN_I2C7:
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return "I2C7";
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/* Storage */
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case SDCARD_DEVFN:
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case PCH_DEVFN_SDCARD:
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return "SDCD";
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case EMMC_DEVFN:
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case PCH_DEVFN_EMMC:
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return "EMMC";
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case SDIO_DEVFN:
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case PCH_DEVFN_SDIO:
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return "SDIO";
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/* PCIe */
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case PCIEB0_DEVFN:
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case PCH_DEVFN_PCIE1:
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return "RP01";
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}
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@ -205,15 +205,15 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
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static void pcie_override_devicetree_after_silicon_init(void)
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{
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pcie_update_device_tree(PCIEA0_DEVFN, 4);
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pcie_update_device_tree(PCIEB0_DEVFN, 2);
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pcie_update_device_tree(PCH_DEVFN_PCIE1, 4);
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pcie_update_device_tree(PCH_DEVFN_PCIE5, 2);
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}
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/* Configure package power limits */
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static void set_power_limits(void)
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{
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static struct soc_intel_apollolake_config *cfg;
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struct device *dev = NB_DEV_ROOT;
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struct device *dev = SA_DEV_ROOT;
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msr_t rapl_msr_reg, limit;
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uint32_t power_unit;
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uint32_t tdp, min_power, max_power;
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@ -329,97 +329,97 @@ static void soc_final(void *data)
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static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
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{
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switch (dev->path.pci.devfn) {
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case ISH_DEVFN:
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case PCH_DEVFN_ISH:
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silconfig->IshEnable = 0;
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break;
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case SATA_DEVFN:
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case PCH_DEVFN_SATA:
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silconfig->EnableSata = 0;
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break;
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case PCIEB0_DEVFN:
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case PCH_DEVFN_PCIE5:
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silconfig->PcieRootPortEn[0] = 0;
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silconfig->PcieRpHotPlug[0] = 0;
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break;
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case PCIEB1_DEVFN:
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case PCH_DEVFN_PCIE6:
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silconfig->PcieRootPortEn[1] = 0;
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silconfig->PcieRpHotPlug[1] = 0;
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break;
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case PCIEA0_DEVFN:
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case PCH_DEVFN_PCIE1:
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silconfig->PcieRootPortEn[2] = 0;
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silconfig->PcieRpHotPlug[2] = 0;
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break;
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case PCIEA1_DEVFN:
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case PCH_DEVFN_PCIE2:
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silconfig->PcieRootPortEn[3] = 0;
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silconfig->PcieRpHotPlug[3] = 0;
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break;
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case PCIEA2_DEVFN:
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case PCH_DEVFN_PCIE3:
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silconfig->PcieRootPortEn[4] = 0;
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silconfig->PcieRpHotPlug[4] = 0;
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break;
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case PCIEA3_DEVFN:
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case PCH_DEVFN_PCIE4:
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silconfig->PcieRootPortEn[5] = 0;
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silconfig->PcieRpHotPlug[5] = 0;
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break;
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case XHCI_DEVFN:
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case PCH_DEVFN_XHCI:
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silconfig->Usb30Mode = 0;
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break;
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case XDCI_DEVFN:
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case PCH_DEVFN_XDCI:
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silconfig->UsbOtg = 0;
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break;
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case LPSS_DEVFN_I2C0:
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case PCH_DEVFN_I2C0:
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silconfig->I2c0Enable = 0;
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break;
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case LPSS_DEVFN_I2C1:
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case PCH_DEVFN_I2C1:
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silconfig->I2c1Enable = 0;
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break;
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case LPSS_DEVFN_I2C2:
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case PCH_DEVFN_I2C2:
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silconfig->I2c2Enable = 0;
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break;
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case LPSS_DEVFN_I2C3:
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case PCH_DEVFN_I2C3:
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silconfig->I2c3Enable = 0;
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break;
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case LPSS_DEVFN_I2C4:
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case PCH_DEVFN_I2C4:
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silconfig->I2c4Enable = 0;
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break;
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case LPSS_DEVFN_I2C5:
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case PCH_DEVFN_I2C5:
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silconfig->I2c5Enable = 0;
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break;
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case LPSS_DEVFN_I2C6:
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case PCH_DEVFN_I2C6:
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silconfig->I2c6Enable = 0;
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break;
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case LPSS_DEVFN_I2C7:
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case PCH_DEVFN_I2C7:
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silconfig->I2c7Enable = 0;
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break;
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case LPSS_DEVFN_UART0:
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case PCH_DEVFN_UART0:
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silconfig->Hsuart0Enable = 0;
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break;
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case LPSS_DEVFN_UART1:
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case PCH_DEVFN_UART1:
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silconfig->Hsuart1Enable = 0;
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break;
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case LPSS_DEVFN_UART2:
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case PCH_DEVFN_UART2:
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silconfig->Hsuart2Enable = 0;
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break;
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case LPSS_DEVFN_UART3:
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case PCH_DEVFN_UART3:
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silconfig->Hsuart3Enable = 0;
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break;
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case LPSS_DEVFN_SPI0:
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case PCH_DEVFN_SPI0:
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silconfig->Spi0Enable = 0;
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break;
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case LPSS_DEVFN_SPI1:
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case PCH_DEVFN_SPI1:
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silconfig->Spi1Enable = 0;
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break;
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case LPSS_DEVFN_SPI2:
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case PCH_DEVFN_SPI2:
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silconfig->Spi2Enable = 0;
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break;
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case SDCARD_DEVFN:
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case PCH_DEVFN_SDCARD:
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silconfig->SdcardEnabled = 0;
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break;
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case EMMC_DEVFN:
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case PCH_DEVFN_EMMC:
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silconfig->eMMCEnabled = 0;
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break;
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case SDIO_DEVFN:
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case PCH_DEVFN_SDIO:
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silconfig->SdioEnabled = 0;
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break;
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case SMBUS_DEVFN:
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case PCH_DEVFN_SMBUS:
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silconfig->SmbusEnable = 0;
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break;
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default:
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@ -432,7 +432,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
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static void parse_devicetree(FSP_S_CONFIG *silconfig)
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{
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struct device *dev = NB_DEV_ROOT;
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struct device *dev = SA_DEV_ROOT;
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if (!dev) {
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printk(BIOS_ERR, "Could not find root device\n");
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@ -454,7 +454,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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/* Load VBT before devicetree-specific config. */
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silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
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struct device *dev = NB_DEV_ROOT;
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struct device *dev = SA_DEV_ROOT;
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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