sravan/system76-coreboot
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The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of

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code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger
2008-10-01 12:52:52 +00:00
parent dc65196f8f
commit 2ee6779a64
166 changed files with 326 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -522,7 +522,7 @@ static void setup_remote_node(u8 node)
printk_debug("setup_remote_node: %02x", node);
/* copy the default resource map from node 0 */
for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
u32 value;
u16 reg;
reg = pci_reg[i];
@ -852,7 +852,7 @@ void cpuSetAMDMSR(void)
revision = mctGetLogicalCPUID(0xFF);
platform = get_platform_type();
for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) {
for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
if ((fam10_msr_default[i].revision & revision) &&
(fam10_msr_default[i].platform & platform)) {
msr = rdmsr(fam10_msr_default[i].msr);
@ -889,7 +889,7 @@ void cpuSetAMDPCI(u8 node)
AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */
for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) {
for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
if ((fam10_pci_default[i].revision & revision) &&
(fam10_pci_default[i].platform & platform)) {
val = pci_read_config32(NODE_PCI(node,
@ -903,7 +903,7 @@ void cpuSetAMDPCI(u8 node)
}
}
for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) {
for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
if ((fam10_htphy_default[i].revision & revision) &&
(fam10_htphy_default[i].platform & platform)) {
/* HT Phy settings either apply to both sublinks or have

2
src/cpu/amd/sc520/sc520.c
View File

@ -151,7 +151,7 @@ static void pci_domain_set_resources(device_t dev)
// int i;
int idx;
#if 0
for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.

2
src/cpu/emulation/qemu-x86/northbridge.c
View File

@ -80,7 +80,7 @@ static void pci_domain_set_resources(device_t dev)
unsigned char rambits;
int i, idx;
for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.