sravan/system76-coreboot
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The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of

Browse Source 
code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger
2008-10-01 12:52:52 +00:00
parent dc65196f8f
commit 2ee6779a64
166 changed files with 326 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/southbridge/amd/amd8111/amd8111_lpc.c
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@@ -10,6 +10,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "amd8111.h"
#define NMI_OFF 0
@@ -77,7 +78,7 @@ static void setup_ioapic(void)
ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid);
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;

3
src/southbridge/amd/cs5536/cs5536.c
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@@ -29,6 +29,7 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/vr.h>
#include <cpu/amd/geode_post_code.h>
#include <stdlib.h>
#include "chip.h"
#include "cs5536.h"
@@ -93,7 +94,7 @@ struct FLASH_DEVICE FlashInitTable[] = {
{FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */
};
#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
uint32_t FlashPort[] = {
MDD_LBAR_FLSH0,

3
src/southbridge/amd/sb600/sb600_sm.c
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@@ -27,6 +27,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "sb600.h"
#include "sb600_smbus.c"
@@ -101,7 +102,7 @@ static void setup_ioapic(unsigned long ioapic_base)
l = (unsigned long *)ioapic_base;
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;

6
src/southbridge/nvidia/ck804/ck804_early_setup.c
View File

@@ -102,7 +102,7 @@ static void ck804_early_set_port(void)
#endif
};
setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]));
setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));
}
@@ -121,7 +121,7 @@ static void ck804_early_clear_port(void)
#endif
};
setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]));
setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));
}
@@ -324,7 +324,7 @@ static void ck804_early_setup(void)
setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0]));
setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf));
setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);

12
src/southbridge/nvidia/ck804/ck804_early_setup_car.c
View File

@@ -105,12 +105,12 @@ static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *i
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf,
sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
ARRAY_SIZE(ctrl_devport_conf),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_b,
sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
ARRAY_SIZE(ctrl_devport_conf_b),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
}
@@ -132,12 +132,12 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf_clear,
sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
ARRAY_SIZE(ctrl_devport_conf_clear),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_clear_b,
sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
ARRAY_SIZE(ctrl_devport_conf_clear_b),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
@@ -327,13 +327,13 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_b
for(j=0; j<ck804_num; j++) {
if(busn[j] == 0) {
setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master),
PCI_DEV(busn[0],0,0), io_base[0]);
continue;
}
setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave),
PCI_DEV(busn[j],0,0), io_base[j]);
}

3
src/southbridge/nvidia/ck804/ck804_lpc.c
View File

@@ -15,6 +15,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "ck804.h"
#define CK804_CHIP_REV 2
@@ -82,7 +83,7 @@ static void setup_ioapic(unsigned long ioapic_base)
l = (unsigned long *) ioapic_base;
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;

14
src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
View File

@@ -106,7 +106,7 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *d
int j;
for(j = 0; j < mcp55_num; j++ ) {
setup_resource_map_offset(ctrl_devport_conf,
sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
ARRAY_SIZE(ctrl_devport_conf),
PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
}
}
@@ -123,7 +123,7 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned
int j;
for(j = 0; j < mcp55_num; j++ ) {
setup_resource_map_offset(ctrl_devport_conf_clear,
sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
ARRAY_SIZE(ctrl_devport_conf_clear),
PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
}
@@ -327,23 +327,23 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
for(j=0; j<mcp55_num; j++) {
mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
for(i=0; i<3; i++) { // three SATA
setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1),
PCI_DEV(busn[j], devn[j], i), io_base[j]);
}
if(busn[j] == 0) {
setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]),
setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
if( (busn[j] == 0) && (mcp55_num>1) ) {
setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}
setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2),
PCI_DEV(busn[j], devn[j], 0), io_base[j]);
}

3
src/southbridge/nvidia/mcp55/mcp55_lpc.c
View File

@@ -34,6 +34,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "mcp55.h"
#define NMI_OFF 0
@@ -106,7 +107,7 @@ static void setup_ioapic(unsigned long ioapic_base, int master)
l = (unsigned long *) ioapic_base;
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;

3
src/southbridge/sis/sis966/sis966_lpc.c
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@@ -36,6 +36,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "sis966.h"
#include <pc80/keyboard.h>
@@ -102,7 +103,7 @@ static void setup_ioapic(unsigned long ioapic_base)
l = (unsigned long *) ioapic_base;
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
l[0] = (a->reg * 2) + 0x10;
l[4] = a->value_low;