intel/gm45: new northbridge

The code supports DDR3 boards only. RAM init for DDR2 is sufficiently
different that it requires separate code, and we have no boards to
test that.

Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/northbridge/intel/gm45/Makefile.inc

@@ -0,0 +1,39 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 secunet Security Networks AG
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+romstage-y += early_init.c
+romstage-y += early_reset.c
+romstage-y += delay.c
+romstage-y += raminit.c
+romstage-y += raminit_rcomp_calibration.c
+romstage-y += raminit_receive_enable_calibration.c
+romstage-y += raminit_read_write_training.c
+romstage-y += pcie.c
+romstage-y += thermal.c
+romstage-y += igd.c
+romstage-y += pm.c
+romstage-y += ram_calc.c
+romstage-$(CONFIG_IOMMU) += iommu.c
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+driver-y += ram_calc.c
+driver-y += northbridge.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += delay.c