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arm(64): Globally replace writel(v, a) with write32(a, v)

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This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner
2015-02-19 14:51:15 -08:00
committed by Patrick Georgi
parent 1f60f971fc
commit 2f37bd6551
131 changed files with 2504 additions and 2638 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/cpu/allwinner/a10/clock.c
View File

@@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 |= 1 << (periph & 0x1f);
writel(reg32, addr);
write32(addr, reg32);
}
/**
@@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 &= ~(1 << (periph & 0x1f));
writel(reg32, addr);
write32(addr, reg32);
}
/**
@@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p)
reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) |
PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p));
reg32 |= PLL5_PLL_ENABLE;
writel(reg32, &ccm->pll5_cfg);
write32(&ccm->pll5_cfg, reg32);
}
/**
@@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= clksel_bits & CPU_CLK_SRC_MASK;
writel(reg32, &ccm->cpu_ahb_apb0_cfg);
write32(&ccm->cpu_ahb_apb0_cfg, reg32);
}
static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
@@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK;
reg32 |= (ahb_exp << 4) & AHB_DIV_MASK;
reg32 |= (apb0_exp << 8) & APB0_DIV_MASK;
writel(reg32, &ccm->cpu_ahb_apb0_cfg);
write32(&ccm->cpu_ahb_apb0_cfg, reg32);
}
static void spin_delay(u32 loops)
@@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
change_sys_divisors(axi, ahb_exp, apb0_exp);
/* Configure PLL1 at the desired frequency */
writel(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
write32(&ccm->pll1_cfg, pll1_table[i].pll1_cfg);
spin_delay(8);
cpu_clk_src_switch(CPU_CLK_SRC_PLL1);

2
src/cpu/allwinner/a10/gpio.c
View File

@@ -76,7 +76,7 @@ void gpio_write(u8 port, u32 val)
if ((port > GPS))
return;
writel(val, &gpio->port[port].dat);
write32(&gpio->port[port].dat, val);
}
/**

4
src/cpu/allwinner/a10/pinmux.c
View File

@@ -33,7 +33,7 @@ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func)
reg32 = read32(&gpio->port[port].cfg[reg]);
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
writel(reg32, &gpio->port[port].cfg[reg]);
write32(&gpio->port[port].cfg[reg], reg32);
}
/**
@@ -74,6 +74,6 @@ void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func)
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
}
writel(reg32, &gpio->port[port].cfg[reg]);
write32(&gpio->port[port].cfg[reg], reg32);
}
}

28
src/cpu/allwinner/a10/raminit.c
View File

@@ -118,7 +118,7 @@ static void mctl_configure_hostport(void)
u32 i;
for (i = 0; i < 32; i++)
writel(hpcr_value[i], &dram->hpcr[i]);
write32(&dram->hpcr[i], hpcr_value[i]);
}
static void mctl_setup_dram_clock(u32 clk)
@@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk)
tmp_val = tmp_val * 9 - 200;
reg32 |= tmp_val << 8;
reg32 |= 0x8 << 24;
writel(reg32, &dram->drr);
write32(&dram->drr, reg32);
} else {
writel(0x0, &dram->drr);
write32(&dram->drr, 0x0);
}
}
@@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para)
a1x_gate_dram_clock_output();
/* select dram controller 1 */
writel(DRAM_CSEL_MAGIC, &dram->csel);
write32(&dram->csel, DRAM_CSEL_MAGIC);
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
@@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
reg32 |= DRAM_DCR_CMD_RANK_ALL;
reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
writel(reg32, &dram->dcr);
write32(&dram->dcr, reg32);
/* dram clock on */
a1x_ungate_dram_clock_output();
@@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para)
reg32 = ((para->zq) >> 8) & 0xfffff;
reg32 |= ((para->zq) & 0xff) << 20;
reg32 |= (para->zq) & 0xf0000000;
writel(reg32, &dram->zqcr0);
write32(&dram->zqcr0, reg32);
/* set I/O configure register */
reg32 = 0x00cc0000;
reg32 |= (para->odt_en) & 0x3;
reg32 |= ((para->odt_en) & 0x3) << 30;
writel(reg32, &dram->iocr);
write32(&dram->iocr, reg32);
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock);
/* set timing parameters */
writel(para->tpr0, &dram->tpr0);
writel(para->tpr1, &dram->tpr1);
writel(para->tpr2, &dram->tpr2);
write32(&dram->tpr0, para->tpr0);
write32(&dram->tpr1, para->tpr1);
write32(&dram->tpr2, para->tpr2);
if (para->type == DRAM_MEMORY_TYPE_DDR3) {
reg32 = DRAM_MR_BURST_LENGTH(0x0);
@@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_MR_CAS_LAT(para->cas);
reg32 |= DRAM_MR_WRITE_RECOVERY(0x5);
}
writel(reg32, &dram->mr);
write32(&dram->mr, reg32);
writel(para->emr1, &dram->emr);
writel(para->emr2, &dram->emr2);
writel(para->emr3, &dram->emr3);
write32(&dram->emr, para->emr1);
write32(&dram->emr2, para->emr2);
write32(&dram->emr3, para->emr3);
/* set DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);

6
src/cpu/allwinner/a10/timer.c
View File

@@ -24,13 +24,13 @@ void init_timer(void)
{
u32 reg32;
/* Load the timer rollover value */
writel(0xffffffff, &tmr0->interval);
write32(&tmr0->interval, 0xffffffff);
/* Configure the timer to run from 24MHz oscillator, no prescaler */
reg32 = TIMER_CTRL_PRESC_DIV_EXP(0);
reg32 |= TIMER_CTRL_CLK_SRC_OSC24M;
reg32 |= TIMER_CTRL_RELOAD;
reg32 |= TIMER_CTRL_TMR_EN;
writel(reg32, &tmr0->ctrl);
write32(&tmr0->ctrl, reg32);
}
void udelay(unsigned usec)
@@ -61,6 +61,6 @@ void udelay(unsigned usec)
*/
u8 a1x_get_cpu_chip_revision(void)
{
writel(0, &timer_module->cpu_cfg);
write32(&timer_module->cpu_cfg, 0);
return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
}

14
src/cpu/allwinner/a10/twi.c
View File

@@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz)
/* Pre-divide the clock by 8 */
n = 3;
m = (apb_clk >> n) / speed_hz;
writel(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
write32(&twi->clk, TWI_CLK_M(m) | TWI_CLK_N(n));
}
void a1x_twi_init(u8 bus, u32 speed_hz)
@@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
configure_clock(twi, speed_hz);
/* Enable the I²C bus */
writel(TWI_CTL_BUS_EN, &twi->ctl);
write32(&twi->ctl, TWI_CTL_BUS_EN);
/* Issue soft reset */
writel(1, &twi->reset);
write32(&twi->reset, 1);
while (i-- && read32(&twi->reset))
udelay(1);
@@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
static void clear_interrupt_flag(struct a1x_twi *twi)
{
writel(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
write32(&twi->ctl, read32(&twi->ctl) & ~TWI_CTL_INT_FLAG);
}
static void i2c_send_data(struct a1x_twi *twi, u8 data)
{
writel(data, &twi->data);
write32(&twi->data, data);
clear_interrupt_flag(twi);
}
@@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_START;
writel(reg32, &twi->ctl);
write32(&twi->ctl, reg32);
/* M_START is automatically cleared after condition is transmitted */
i = TWI_TIMEOUT;
@@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_STOP;
writel(reg32, &twi->ctl);
write32(&twi->ctl, reg32);
}
static int i2c_read(struct a1x_twi *twi, uint8_t chip,

12
src/cpu/allwinner/a10/uart.c
View File

@@ -22,10 +22,10 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
div = (u16) uart_baudrate_divisor(baud_rate,
uart_platform_refclk(), 16);
/* Enable access to Divisor Latch register */
writel(UART8250_LCR_DLAB, &uart->lcr);
write32(&uart->lcr, UART8250_LCR_DLAB);
/* Set baudrate */
writel((div >> 8) & 0xff, &uart->dlh);
writel(div & 0xff, &uart->dll);
write32(&uart->dlh, (div >> 8) & 0xff);
write32(&uart->dll, div & 0xff);
/* Set line control */
reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK;
switch (parity) {
@@ -40,12 +40,12 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
default:
break;
}
writel(reg32, &uart->lcr);
write32(&uart->lcr, reg32);
}
static void a10_uart_enable_fifos(struct a10_uart *uart)
{
writel(UART8250_FCR_FIFO_EN, &uart->fcr);
write32(&uart->fcr, UART8250_FCR_FIFO_EN);
}
static int tx_fifo_full(struct a10_uart *uart)
@@ -83,7 +83,7 @@ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
{
while (tx_fifo_full(uart)) ;
return writel(data, &uart->thr);
return write32(&uart->thr, data);
}

158
src/cpu/ti/am335x/pinmux.c
View File

@@ -28,163 +28,163 @@ static struct am335x_pinmux_regs *regs =
void am335x_pinmux_uart0(void)
{
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart0_rxd);
writel(MODE(0) | PULLUDEN, &regs->uart0_txd);
write32(&regs->uart0_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->uart0_txd, MODE(0) | PULLUDEN);
}
void am335x_pinmux_uart1(void)
{
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart1_rxd);
writel(MODE(0) | PULLUDEN, &regs->uart1_txd);
write32(&regs->uart1_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->uart1_txd, MODE(0) | PULLUDEN);
}
void am335x_pinmux_uart2(void)
{
// UART2_RXD
writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_sclk);
write32(&regs->spi0_sclk, MODE(1) | PULLUP_EN | RXACTIVE);
// UART2_TXD
writel(MODE(1) | PULLUDEN, &regs->spi0_d0);
write32(&regs->spi0_d0, MODE(1) | PULLUDEN);
}
void am335x_pinmux_uart3(void)
{
// UART3_RXD
writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_cs1);
write32(&regs->spi0_cs1, MODE(1) | PULLUP_EN | RXACTIVE);
// UART3_TXD
writel(MODE(1) | PULLUDEN, &regs->ecap0_in_pwm0_out);
write32(&regs->ecap0_in_pwm0_out, MODE(1) | PULLUDEN);
}
void am335x_pinmux_uart4(void)
{
// UART4_RXD
writel(MODE(6) | PULLUP_EN | RXACTIVE, &regs->gpmc_wait0);
write32(&regs->gpmc_wait0, MODE(6) | PULLUP_EN | RXACTIVE);
// UART4_TXD
writel(MODE(6) | PULLUDEN, &regs->gpmc_wpn);
write32(&regs->gpmc_wpn, MODE(6) | PULLUDEN);
}
void am335x_pinmux_uart5(void)
{
// UART5_RXD
writel(MODE(4) | PULLUP_EN | RXACTIVE, &regs->lcd_data9);
write32(&regs->lcd_data9, MODE(4) | PULLUP_EN | RXACTIVE);
// UART5_TXD
writel(MODE(4) | PULLUDEN, &regs->lcd_data8);
write32(&regs->lcd_data8, MODE(4) | PULLUDEN);
}
void am335x_pinmux_mmc0(int cd, int sk_evm)
{
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat0);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat1);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat2);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat3);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_clk);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_cmd);
write32(&regs->mmc0_dat0, MODE(0) | RXACTIVE | PULLUP_EN);
write32(&regs->mmc0_dat1, MODE(0) | RXACTIVE | PULLUP_EN);
write32(&regs->mmc0_dat2, MODE(0) | RXACTIVE | PULLUP_EN);
write32(&regs->mmc0_dat3, MODE(0) | RXACTIVE | PULLUP_EN);
write32(&regs->mmc0_clk, MODE(0) | RXACTIVE | PULLUP_EN);
write32(&regs->mmc0_cmd, MODE(0) | RXACTIVE | PULLUP_EN);
if (!sk_evm) {
// MMC0_WP
writel(MODE(4) | RXACTIVE, &regs->mcasp0_aclkr);
write32(&regs->mcasp0_aclkr, MODE(4) | RXACTIVE);
}
if (cd) {
// MMC0_CD
writel(MODE(5) | RXACTIVE | PULLUP_EN, &regs->spi0_cs1);
write32(&regs->spi0_cs1, MODE(5) | RXACTIVE | PULLUP_EN);
}
}
void am335x_pinmux_mmc1(void)
{
// MMC1_DAT0
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad0);
write32(&regs->gpmc_ad0, MODE(1) | RXACTIVE | PULLUP_EN);
// MMC1_DAT1
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad1);
write32(&regs->gpmc_ad1, MODE(1) | RXACTIVE | PULLUP_EN);
// MMC1_DAT2
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad2);
write32(&regs->gpmc_ad2, MODE(1) | RXACTIVE | PULLUP_EN);
// MMC1_DAT3
writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad3);
write32(&regs->gpmc_ad3, MODE(1) | RXACTIVE | PULLUP_EN);
// MMC1_CLK
writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn1);
write32(&regs->gpmc_csn1, MODE(2) | RXACTIVE | PULLUP_EN);
// MMC1_CMD
writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn2);
write32(&regs->gpmc_csn2, MODE(2) | RXACTIVE | PULLUP_EN);
// MMC1_WP
writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn0);
write32(&regs->gpmc_csn0, MODE(7) | RXACTIVE | PULLUP_EN);
// MMC1_CD
writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_advn_ale);
write32(&regs->gpmc_advn_ale, MODE(7) | RXACTIVE | PULLUP_EN);
}
void am335x_pinmux_i2c0(void)
{
writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_sda);
writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_scl);
write32(&regs->i2c0_sda, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
write32(&regs->i2c0_scl, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
}
void am335x_pinmux_i2c1(void)
{
// I2C_DATA
writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_d1);
write32(&regs->spi0_d1, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
// I2C_SCLK
writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_cs0);
write32(&regs->spi0_cs0, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
}
void am335x_pinmux_spi0(void)
{
writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_sclk);
writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_d0);
writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_d1);
writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_cs0);
write32(&regs->spi0_sclk, MODE(0) | RXACTIVE | PULLUDEN);
write32(&regs->spi0_d0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
write32(&regs->spi0_d1, MODE(0) | RXACTIVE | PULLUDEN);
write32(&regs->spi0_cs0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
}
void am335x_pinmux_gpio0_7(void)
{
writel(MODE(7) | PULLUDEN, &regs->ecap0_in_pwm0_out);
write32(&regs->ecap0_in_pwm0_out, MODE(7) | PULLUDEN);
}
void am335x_pinmux_rgmii1(void)
{
writel(MODE(2), &regs->mii1_txen);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxdv);
writel(MODE(2), &regs->mii1_txd0);
writel(MODE(2), &regs->mii1_txd1);
writel(MODE(2), &regs->mii1_txd2);
writel(MODE(2), &regs->mii1_txd3);
writel(MODE(2), &regs->mii1_txclk);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxclk);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd0);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd1);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd2);
writel(MODE(2) | RXACTIVE, &regs->mii1_rxd3);
write32(&regs->mii1_txen, MODE(2));
write32(&regs->mii1_rxdv, MODE(2) | RXACTIVE);
write32(&regs->mii1_txd0, MODE(2));
write32(&regs->mii1_txd1, MODE(2));
write32(&regs->mii1_txd2, MODE(2));
write32(&regs->mii1_txd3, MODE(2));
write32(&regs->mii1_txclk, MODE(2));
write32(&regs->mii1_rxclk, MODE(2) | RXACTIVE);
write32(&regs->mii1_rxd0, MODE(2) | RXACTIVE);
write32(&regs->mii1_rxd1, MODE(2) | RXACTIVE);
write32(&regs->mii1_rxd2, MODE(2) | RXACTIVE);
write32(&regs->mii1_rxd3, MODE(2) | RXACTIVE);
}
void am335x_pinmux_mii1(void)
{
writel(MODE(0) | RXACTIVE, &regs->mii1_rxerr);
writel(MODE(0), &regs->mii1_txen);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxdv);
writel(MODE(0), &regs->mii1_txd0);
writel(MODE(0), &regs->mii1_txd1);
writel(MODE(0), &regs->mii1_txd2);
writel(MODE(0), &regs->mii1_txd3);
writel(MODE(0) | RXACTIVE, &regs->mii1_txclk);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxclk);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd0);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd1);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd2);
writel(MODE(0) | RXACTIVE, &regs->mii1_rxd3);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mdio_data);
writel(MODE(0) | PULLUP_EN, &regs->mdio_clk);
write32(&regs->mii1_rxerr, MODE(0) | RXACTIVE);
write32(&regs->mii1_txen, MODE(0));
write32(&regs->mii1_rxdv, MODE(0) | RXACTIVE);
write32(&regs->mii1_txd0, MODE(0));
write32(&regs->mii1_txd1, MODE(0));
write32(&regs->mii1_txd2, MODE(0));
write32(&regs->mii1_txd3, MODE(0));
write32(&regs->mii1_txclk, MODE(0) | RXACTIVE);
write32(&regs->mii1_rxclk, MODE(0) | RXACTIVE);
write32(&regs->mii1_rxd0, MODE(0) | RXACTIVE);
write32(&regs->mii1_rxd1, MODE(0) | RXACTIVE);
write32(&regs->mii1_rxd2, MODE(0) | RXACTIVE);
write32(&regs->mii1_rxd3, MODE(0) | RXACTIVE);
write32(&regs->mdio_data, MODE(0) | RXACTIVE | PULLUP_EN);
write32(&regs->mdio_clk, MODE(0) | PULLUP_EN);
}
void am335x_pinmux_nand(void)
{
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad0);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad1);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad2);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad3);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad4);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad5);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad6);
writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad7);
writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->gpmc_wait0);
writel(MODE(7) | PULLUP_EN | RXACTIVE, &regs->gpmc_wpn);
writel(MODE(0) | PULLUDEN, &regs->gpmc_csn0);
writel(MODE(0) | PULLUDEN, &regs->gpmc_advn_ale);
writel(MODE(0) | PULLUDEN, &regs->gpmc_oen_ren);
writel(MODE(0) | PULLUDEN, &regs->gpmc_wen);
writel(MODE(0) | PULLUDEN, &regs->gpmc_be0n_cle);
write32(&regs->gpmc_ad0, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_ad1, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_ad2, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_ad3, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_ad4, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_ad5, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_ad6, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_ad7, MODE(0) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_wait0, MODE(0) | RXACTIVE | PULLUP_EN);
write32(&regs->gpmc_wpn, MODE(7) | PULLUP_EN | RXACTIVE);
write32(&regs->gpmc_csn0, MODE(0) | PULLUDEN);
write32(&regs->gpmc_advn_ale, MODE(0) | PULLUDEN);
write32(&regs->gpmc_oen_ren, MODE(0) | PULLUDEN);
write32(&regs->gpmc_wen, MODE(0) | PULLUDEN);
write32(&regs->gpmc_be0n_cle, MODE(0) | PULLUDEN);
}

52
src/cpu/ti/am335x/uart.c
View File

@@ -42,88 +42,88 @@ static void am335x_uart_init(struct am335x_uart *uart, uint16_t div)
uint16_t lcr_orig, efr_orig, mcr_orig;
/* reset the UART */
writew(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
write16(&uart->sysc, uart->sysc | SYSC_SOFTRESET);
while (!(read16(&uart->syss) & SYSS_RESETDONE))
;
/* 1. switch to register config mode B */
lcr_orig = read16(&uart->lcr);
writew(0xbf, &uart->lcr);
write16(&uart->lcr, 0xbf);
/*
* 2. Set EFR ENHANCED_EN bit. To access this bit, registers must
* be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1.
*/
efr_orig = read16(&uart->efr);
writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
write16(&uart->efr, efr_orig | EFR_ENHANCED_EN);
/* 3. Switch to register config mode A */
writew(0x80, &uart->lcr);
write16(&uart->lcr, 0x80);
/* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */
mcr_orig = read16(&uart->mcr);
writew(mcr_orig | MCR_TCR_TLR, &uart->mcr);
write16(&uart->mcr, mcr_orig | MCR_TCR_TLR);
/* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */
writew(FCR_FIFO_EN, &uart->fcr);
write16(&uart->fcr, FCR_FIFO_EN);
/* 6. Switch to configuration mode B */
writew(0xbf, &uart->lcr);
write16(&uart->lcr, 0xbf);
/* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */
/* 9. Restore original EFR value */
writew(efr_orig, &uart->efr);
write16(&uart->efr, efr_orig);
/* 10. Switch to config mode A */
writew(0x80, &uart->lcr);
write16(&uart->lcr, 0x80);
/* 11. Restore original MCR value */
writew(mcr_orig, &uart->mcr);
write16(&uart->mcr, mcr_orig);
/* 12. Restore original LCR value */
writew(lcr_orig, &uart->lcr);
write16(&uart->lcr, lcr_orig);
/* Protocol, baud rate and interrupt settings */
/* 1. Disable UART access to DLL and DLH registers */
writew(read16(&uart->mdr1) | 0x7, &uart->mdr1);
write16(&uart->mdr1, read16(&uart->mdr1) | 0x7);
/* 2. Switch to config mode B */
writew(0xbf, &uart->lcr);
write16(&uart->lcr, 0xbf);
/* 3. Enable access to IER[7:4] */
writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
write16(&uart->efr, efr_orig | EFR_ENHANCED_EN);
/* 4. Switch to operational mode */
writew(0x0, &uart->lcr);
write16(&uart->lcr, 0x0);
/* 5. Clear IER */
writew(0x0, &uart->ier);
write16(&uart->ier, 0x0);
/* 6. Switch to config mode B */
writew(0xbf, &uart->lcr);
write16(&uart->lcr, 0xbf);
/* 7. Set dll and dlh to the desired values (table 19-25) */
writew((div >> 8), &uart->dlh);
writew((div & 0xff), &uart->dll);
write16(&uart->dlh, (div >> 8));
write16(&uart->dll, (div & 0xff));
/* 8. Switch to operational mode to access ier */
writew(0x0, &uart->lcr);
write16(&uart->lcr, 0x0);
/* 9. Clear ier to disable all interrupts */
writew(0x0, &uart->ier);
write16(&uart->ier, 0x0);
/* 10. Switch to config mode B */
writew(0xbf, &uart->lcr);
write16(&uart->lcr, 0xbf);
/* 11. Restore efr */
writew(efr_orig, &uart->efr);
write16(&uart->efr, efr_orig);
/* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */
writew(0x3, &uart->lcr);
write16(&uart->lcr, 0x3);
/* 13. Load the new UART mode */
writew(0x0, &uart->mdr1);
write16(&uart->mdr1, 0x0);
}
/*
@@ -145,7 +145,7 @@ static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data)
{
while (!(read16(&uart->lsr) & LSR_TXFIFOE));
return writeb(data, &uart->thr);
return write8(&uart->thr, data);
}
unsigned int uart_platform_refclk(void)