arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/ti/beaglebone/bootblock.c

@@ -29,7 +29,7 @@ void bootblock_mainboard_init(void)
 	void *uart_clock_ctrl = NULL;
 
 	/* Enable the GPIO module */
-	writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac));
+	write32((uint32_t *)(0x44e00000 + 0xac), (0x2 << 0) | (1 << 18));
 
 	/* Disable interrupts from these GPIOs */
 	setbits_le32((uint32_t *)(0x4804c000 + 0x3c), 0xf << 21);
@@ -62,7 +62,7 @@ void bootblock_mainboard_init(void)
 		uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38);
 	}
 	if (uart_clock_ctrl)
-		writel(0x2, uart_clock_ctrl);
+		write32(uart_clock_ctrl, 0x2);
 
 	/* Start monotonic timer */
 	//rtc_start();