arch/arm: Pass cbmem_top to ramstage via calling argument

This solution is very generic and can in principle be implemented on
all arch/soc.

Instead trying to figure out which files can be removed from stages
and which cbmem_top implementations need with preprocessor, rename all
cbmem_top implementation to cbmem_top_romstage.

Mechanisms set in place to pass on information from rom- to ram-stage
will be placed in a followup commit.

Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/arch/arm/Kconfig

@@ -17,6 +17,7 @@ config ARCH_ROMSTAGE_ARM
 config ARCH_RAMSTAGE_ARM
 	bool
 	select ARCH_ARM
+	select RAMSTAGE_CBMEM_TOP_ARG
 
 source src/arch/arm/armv4/Kconfig
 source src/arch/arm/armv7/Kconfig

src/arch/arm/include/arch/stages.h

@@ -14,8 +14,9 @@
 #ifndef __ARCH_STAGES_H
 #define __ARCH_STAGES_H
 
+#include <stdint.h>
 #include <main_decl.h>
 
-void stage_entry(void);
+void stage_entry(uintptr_t stage_arg);
 
 #endif

src/arch/arm/stages.c

@@ -22,13 +22,16 @@
  * .text.stage_entry section created by -ffunction-sections).
  */
 
+#include <cbmem.h>
 #include <arch/stages.h>
 #include <arch/cache.h>
 
 /**
  * generic stage entry point. override this if board specific code is needed.
  */
-__weak void stage_entry(void)
+__weak void stage_entry(uintptr_t stage_arg)
 {
+	if (!ENV_ROMSTAGE_OR_BEFORE)
+		_cbmem_top_ptr = stage_arg;
 	main();
 }

src/cpu/ti/am335x/Makefile.inc

@@ -10,7 +10,6 @@ romstage-y	+= cbmem.c
 ramstage-y	+= dmtimer.c
 ramstage-y	+= monotonic_timer.c
 ramstage-y	+= nand.c
-ramstage-y	+= cbmem.c
 
 bootblock-y	+= uart.c
 romstage-y	+= uart.c

src/mainboard/emulation/qemu-armv7/Makefile.inc

@@ -15,7 +15,6 @@
 romstage-y += romstage.c
 
 romstage-y += cbmem.c
-ramstage-y += cbmem.c
 
 bootblock-y += media.c
 romstage-y += media.c

src/soc/nvidia/tegra124/Makefile.inc

@@ -46,7 +46,6 @@ romstage-y += ../tegra/pinmux.c
 romstage-y += cache.c
 romstage-y += uart.c
 
-ramstage-y += cbmem.c
 ramstage-y += clock.c
 ramstage-y += display.c
 ramstage-y += dma.c

src/soc/nvidia/tegra124/verstage.c

@@ -45,7 +45,7 @@ void verstage_mainboard_init(void)
 	early_mainboard_init();
 }
 
-void stage_entry(void)
+void stage_entry(uintptr_t unused)
 {
 	asm volatile ("bl arm_init_caches"
 		      : : : "r0", "r1", "r2", "r3", "r4", "r5", "ip");

src/soc/rockchip/rk3288/Makefile.inc

@@ -18,7 +18,6 @@ ifeq ($(CONFIG_SOC_ROCKCHIP_RK3288),y)
 IDBTOOL = util/rockchip/make_idb.py
 
 bootblock-y += bootblock.c
-bootblock-y += ../common/cbmem.c
 bootblock-y += ../common/uart.c
 bootblock-y += timer.c
 bootblock-y += clock.c
@@ -55,7 +54,6 @@ romstage-y += tsadc.c
 romstage-y += ../common/i2c.c
 
 ramstage-y += soc.c
-ramstage-y += ../common/cbmem.c
 ramstage-y += timer.c
 ramstage-y += ../common/i2c.c
 ramstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c

src/soc/samsung/exynos5250/Makefile.inc

@@ -40,7 +40,6 @@ ramstage-y += i2c.c
 ramstage-y += dp-reg.c
 ramstage-y += fb.c
 ramstage-y += usb.c
-ramstage-y += cbmem.c
 
 CPPFLAGS_common += -Isrc/soc/samsung/exynos5250/include/
 

src/soc/samsung/exynos5420/Makefile.inc

@@ -40,7 +40,6 @@ ramstage-y += gpio.c
 ramstage-y += i2c.c
 ramstage-y += dp.c dp_lowlevel.c fimd.c
 ramstage-y += usb.c
-ramstage-y += cbmem.c
 
 rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c