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soc/amd: factor out common family 17h&19h TSC and monotonic timer code

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The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.

Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held
2020-12-04 17:31:10 +01:00
parent 0a93f7a7e9
commit 2f5c759077
6 changed files with 32 additions and 14 deletions
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4
src/soc/amd/picasso/Kconfig
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@@ -24,10 +24,7 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC
select HAVE_EM100_SUPPORT
select HAVE_USBDEBUG_OPTIONS
select COLLECT_TIMESTAMPS_NO_TSC
select SOC_AMD_COMMON_BLOCK_SPI
select TSC_SYNC_LFENCE
select UDELAY_TSC
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
@@ -44,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_SMU
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
select PROVIDES_ROM_SHARING
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH