soc/amd: factor out common family 17h&19h TSC and monotonic timer code
The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the code. Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@@ -3,7 +3,6 @@
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ifeq ($(CONFIG_SOC_AMD_PICASSO),y)
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subdirs-y += ../../../cpu/amd/mtrr/
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/cache
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subdirs-y += ../../../cpu/x86/mtrr
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@@ -17,8 +16,6 @@ bootblock-y += southbridge.c
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bootblock-y += i2c.c
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bootblock-y += uart.c
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bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
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bootblock-y += monotonic_timer.c
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bootblock-y += tsc_freq.c
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bootblock-y += gpio.c
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bootblock-y += config.c
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bootblock-y += reset.c
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@@ -30,8 +27,6 @@ romstage-y += reset.c
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romstage-y += memmap.c
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romstage-y += uart.c
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romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
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romstage-y += monotonic_timer.c
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romstage-y += tsc_freq.c
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romstage-y += aoac.c
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romstage-y += southbridge.c
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romstage-y += psp.c
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@@ -44,8 +39,6 @@ verstage-y += aoac.c
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verstage_x86-y += gpio.c
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verstage_x86-y += uart.c
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verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
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verstage_x86-y += monotonic_timer.c
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verstage_x86-y += tsc_freq.c
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verstage_x86-y += reset.c
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ramstage-y += i2c.c
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@@ -66,8 +59,6 @@ ramstage-y += memmap.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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ramstage-y += uart.c
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ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
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ramstage-y += monotonic_timer.c
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ramstage-y += tsc_freq.c
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ramstage-y += finalize.c
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ramstage-y += soc_util.c
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ramstage-y += psp.c
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@@ -80,8 +71,6 @@ ramstage-y += xhci.c
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ramstage-y += dmi.c
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smm-y += smihandler.c
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smm-y += monotonic_timer.c
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smm-y += tsc_freq.c
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ifeq ($(CONFIG_DEBUG_SMI),y)
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smm-y += uart.c
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smm-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
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