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vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2037

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The headers added are generated as per FSP v2037.
Previous FSP version was v2037.
Changes Include:
- add BootFrequency, RMTBIT, RmtPerTask, RMTLoopCount and
 MrcFastBoot UPDs in Fspm.h
- add EnableFastMsrHwpReq, VbtSize, CpuPcieComplianceTestMode,
 LidStatus and PcieComplianceTestMode UPDs in Fsps.h

BUG=b:178461282,b:180627057
BRANCH=None
TEST=Build and boot ADLRVP

Change-Id: I5496dfebc7b65a94abb31244ef2b400d89d6d444
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50914
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar
2021-02-19 20:22:18 +05:30
committed by Tim Wawrzynczak
parent 437c2baac4
commit 2f67badda6
2 changed files with 166 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

133
src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
View File

@@ -216,7 +216,24 @@ typedef struct {
/** Offset 0x0129 - Reserved
**/
UINT8 Reserved1[7];
UINT8 Reserved1;
/** Offset 0x012A - MRC Fast Boot
Enables/Disable the MRC fast path thru the MRC
$EN_DIS
**/
UINT8 MrcFastBoot;
/** Offset 0x012B - Rank Margin Tool per Task
This option enables the user to execute Rank Margin Tool per major training step
in the MRC.
$EN_DIS
**/
UINT8 RmtPerTask;
/** Offset 0x012C - Reserved
**/
UINT8 Reserved2[4];
/** Offset 0x0130 - Tseg Size
Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
@@ -226,7 +243,7 @@ typedef struct {
/** Offset 0x0134 - Reserved
**/
UINT8 Reserved2[3];
UINT8 Reserved3[3];
/** Offset 0x0137 - Enable SMBus
Enable/disable SMBus controller.
@@ -252,7 +269,7 @@ typedef struct {
/** Offset 0x0149 - Reserved
**/
UINT8 Reserved3[14];
UINT8 Reserved4[14];
/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table
0=Disable/Clear, 1=Enable/Set
@@ -262,7 +279,7 @@ typedef struct {
/** Offset 0x0158 - Reserved
**/
UINT8 Reserved4[40];
UINT8 Reserved5[40];
/** Offset 0x0180 - Disable VT-d
0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
@@ -272,7 +289,7 @@ typedef struct {
/** Offset 0x0181 - Reserved
**/
UINT8 Reserved5[4];
UINT8 Reserved6[4];
/** Offset 0x0185 - Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics.
@@ -290,7 +307,7 @@ typedef struct {
/** Offset 0x0187 - Reserved
**/
UINT8 Reserved6;
UINT8 Reserved7;
/** Offset 0x0188 - Board Type
MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -301,7 +318,7 @@ typedef struct {
/** Offset 0x0189 - Reserved
**/
UINT8 Reserved7[3];
UINT8 Reserved8[3];
/** Offset 0x018C - SA GV
System Agent dynamic frequency support and when enabled memory will be training
@@ -312,7 +329,7 @@ typedef struct {
/** Offset 0x018D - Reserved
**/
UINT8 Reserved8[2];
UINT8 Reserved9[2];
/** Offset 0x018F - Rank Margin Tool
Enable/disable Rank Margin Tool.
@@ -370,7 +387,7 @@ typedef struct {
/** Offset 0x0198 - Reserved
**/
UINT8 Reserved9[2];
UINT8 Reserved10[2];
/** Offset 0x019A - Memory Reference Clock
100MHz, 133MHz.
@@ -380,7 +397,7 @@ typedef struct {
/** Offset 0x019B - Reserved
**/
UINT8 Reserved10[22];
UINT8 Reserved11[22];
/** Offset 0x01B1 - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller
@@ -396,7 +413,7 @@ typedef struct {
/** Offset 0x01B3 - Reserved
**/
UINT8 Reserved11[107];
UINT8 Reserved12[107];
/** Offset 0x021E - IMGU CLKOUT Configuration
The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
@@ -412,7 +429,7 @@ typedef struct {
/** Offset 0x0228 - Reserved
**/
UINT8 Reserved12;
UINT8 Reserved13;
/** Offset 0x0229 - RpClockReqMsgEnable
**/
@@ -424,7 +441,7 @@ typedef struct {
/** Offset 0x0230 - Reserved
**/
UINT8 Reserved13;
UINT8 Reserved14;
/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -524,7 +541,7 @@ typedef struct {
/** Offset 0x0241 - Reserved
**/
UINT8 Reserved14[141];
UINT8 Reserved15[141];
/** Offset 0x02CE - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
@@ -533,7 +550,7 @@ typedef struct {
/** Offset 0x02D6 - Reserved
**/
UINT8 Reserved15[150];
UINT8 Reserved16[150];
/** Offset 0x036C - C6DRAM power gating feature
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
@@ -545,7 +562,7 @@ typedef struct {
/** Offset 0x036D - Reserved
**/
UINT8 Reserved16[5];
UINT8 Reserved17[5];
/** Offset 0x0372 - Hyper Threading Enable/Disable
Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
@@ -555,16 +572,23 @@ typedef struct {
/** Offset 0x0373 - Reserved
**/
UINT8 Reserved17;
UINT8 Reserved18;
/** Offset 0x0374 - CPU ratio value
CPU ratio value. Valid Range 0 to 63
**/
UINT8 CpuRatio;
/** Offset 0x0375 - Reserved
/** Offset 0x0375 - Boot frequency
Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.
1: Maximum non-turbo performance. <b>2: Turbo performance </b>
0:0, 1:1, 2:2
**/
UINT8 Reserved18[2];
UINT8 BootFrequency;
/** Offset 0x0376 - Reserved
**/
UINT8 Reserved19;
/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting
<b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
@@ -575,7 +599,7 @@ typedef struct {
/** Offset 0x0378 - Reserved
**/
UINT8 Reserved19;
UINT8 Reserved20;
/** Offset 0x0379 - Enable or Disable VMX
Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
@@ -585,7 +609,7 @@ typedef struct {
/** Offset 0x037A - Reserved
**/
UINT8 Reserved20[20];
UINT8 Reserved21[20];
/** Offset 0x038E - Enable or Disable TME
Enable or Disable TME; <b>0: Disable</b>; 1: Enable.
@@ -595,7 +619,7 @@ typedef struct {
/** Offset 0x038F - Reserved
**/
UINT8 Reserved21[3];
UINT8 Reserved22[3];
/** Offset 0x0392 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -609,7 +633,7 @@ typedef struct {
/** Offset 0x0394 - Reserved
**/
UINT8 Reserved22[4];
UINT8 Reserved23[4];
/** Offset 0x0398 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -623,7 +647,7 @@ typedef struct {
/** Offset 0x03A0 - Reserved
**/
UINT8 Reserved23[8];
UINT8 Reserved24[8];
/** Offset 0x03A8 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
@@ -637,7 +661,7 @@ typedef struct {
/** Offset 0x03B0 - Reserved
**/
UINT8 Reserved24[625];
UINT8 Reserved25[625];
/** Offset 0x0621 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
@@ -646,7 +670,7 @@ typedef struct {
/** Offset 0x0622 - Reserved
**/
UINT8 Reserved25[3];
UINT8 Reserved26[3];
/** Offset 0x0625 - Usage type for ClkSrc
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
@@ -656,7 +680,7 @@ typedef struct {
/** Offset 0x0637 - Reserved
**/
UINT8 Reserved26[14];
UINT8 Reserved27[14];
/** Offset 0x0645 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
@@ -665,7 +689,7 @@ typedef struct {
/** Offset 0x0657 - Reserved
**/
UINT8 Reserved27[93];
UINT8 Reserved28[93];
/** Offset 0x06B4 - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -675,7 +699,7 @@ typedef struct {
/** Offset 0x06B8 - Reserved
**/
UINT8 Reserved28[2];
UINT8 Reserved29[2];
/** Offset 0x06BA - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
@@ -685,7 +709,7 @@ typedef struct {
/** Offset 0x06BB - Reserved
**/
UINT8 Reserved29[3];
UINT8 Reserved30[3];
/** Offset 0x06BE - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
@@ -710,7 +734,7 @@ typedef struct {
/** Offset 0x06D1 - Reserved
**/
UINT8 Reserved30[3];
UINT8 Reserved31[3];
/** Offset 0x06D4 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -760,7 +784,7 @@ typedef struct {
/** Offset 0x06EB - Reserved
**/
UINT8 Reserved31[13];
UINT8 Reserved32[13];
/** Offset 0x06F8 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
@@ -770,7 +794,7 @@ typedef struct {
/** Offset 0x06F9 - Reserved
**/
UINT8 Reserved32[4];
UINT8 Reserved33[4];
/** Offset 0x06FD - MRC Safe Config
Enables/Disable MRC Safe Config
@@ -828,7 +852,7 @@ typedef struct {
/** Offset 0x0706 - Reserved
**/
UINT8 Reserved33[2];
UINT8 Reserved34[2];
/** Offset 0x0708 - Early Command Training
Enables/Disable Early Command Training
@@ -838,7 +862,17 @@ typedef struct {
/** Offset 0x0709 - Reserved
**/
UINT8 Reserved34[65];
UINT8 Reserved35[58];
/** Offset 0x0743 - Rank Margin Tool Per Bit
Enable/Disable Rank Margin Tool Per Bit
$EN_DIS
**/
UINT8 RMTBIT;
/** Offset 0x0744 - Reserved
**/
UINT8 Reserved36[6];
/** Offset 0x074A - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -848,7 +882,7 @@ typedef struct {
/** Offset 0x074C - Reserved
**/
UINT8 Reserved35[66];
UINT8 Reserved37[66];
/** Offset 0x078E - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
@@ -861,7 +895,7 @@ typedef struct {
/** Offset 0x078F - Reserved
**/
UINT8 Reserved36[2];
UINT8 Reserved38[2];
/** Offset 0x0791 - Safe Mode Support
This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
@@ -871,7 +905,7 @@ typedef struct {
/** Offset 0x0792 - Reserved
**/
UINT8 Reserved37[2];
UINT8 Reserved39[2];
/** Offset 0x0794 - TCSS USB Port Enable
Bitmap for per port enabling
@@ -880,7 +914,16 @@ typedef struct {
/** Offset 0x0795 - Reserved
**/
UINT8 Reserved38[33];
UINT8 Reserved40[3];
/** Offset 0x0798 - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/
UINT8 RMTLoopCount;
/** Offset 0x0799 - Reserved
**/
UINT8 Reserved41[29];
/** Offset 0x07B6 - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -890,7 +933,7 @@ typedef struct {
/** Offset 0x07B7 - Reserved
**/
UINT8 Reserved39[12];
UINT8 Reserved42[12];
/** Offset 0x07C3 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -901,7 +944,7 @@ typedef struct {
/** Offset 0x07C4 - Reserved
**/
UINT8 Reserved40;
UINT8 Reserved43;
/** Offset 0x07C5 - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
@@ -911,7 +954,7 @@ typedef struct {
/** Offset 0x07C6 - Reserved
**/
UINT8 Reserved41[131];
UINT8 Reserved44[131];
/** Offset 0x0849 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
@@ -921,7 +964,7 @@ typedef struct {
/** Offset 0x084A - Reserved
**/
UINT8 Reserved42[292];
UINT8 Reserved45[292];
/** Offset 0x096E - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
@@ -932,7 +975,7 @@ typedef struct {
/** Offset 0x096F - Reserved
**/
UINT8 Reserved43[185];
UINT8 Reserved46[185];
/** Offset 0x0A28 - GPIO Override
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
@@ -943,7 +986,7 @@ typedef struct {
/** Offset 0x0A29 - Reserved
**/
UINT8 Reserved44[23];
UINT8 Reserved47[23];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration

111
src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
View File

@@ -458,7 +458,22 @@ typedef struct {
/** Offset 0x0525 - Reserved
**/
UINT8 Reserved20[16];
UINT8 Reserved20[3];
/** Offset 0x0528 - Intel Graphics VBT (Video BIOS Table) Size
Size of Internal Graphics VBT Image
**/
UINT32 VbtSize;
/** Offset 0x052C - Platform LID Status for LFP Displays.
LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
0: LidClosed, 1: LidOpen
**/
UINT8 LidStatus;
/** Offset 0x052D - Reserved
**/
UINT8 Reserved21[8];
/** Offset 0x0535 - Enable VMD controller
Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
@@ -468,7 +483,7 @@ typedef struct {
/** Offset 0x0536 - Reserved
**/
UINT8 Reserved21[120];
UINT8 Reserved22[120];
/** Offset 0x05AE - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
@@ -482,7 +497,7 @@ typedef struct {
/** Offset 0x05B2 - Reserved
**/
UINT8 Reserved22;
UINT8 Reserved23;
/** Offset 0x05B3 - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
@@ -492,7 +507,7 @@ typedef struct {
/** Offset 0x05B7 - Reserved
**/
UINT8 Reserved23[3];
UINT8 Reserved24[3];
/** Offset 0x05BA - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
@@ -502,7 +517,7 @@ typedef struct {
/** Offset 0x05BC - Reserved
**/
UINT8 Reserved24[7];
UINT8 Reserved25[7];
/** Offset 0x05C3 - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
@@ -512,7 +527,7 @@ typedef struct {
/** Offset 0x05C7 - Reserved
**/
UINT8 Reserved25[200];
UINT8 Reserved26[200];
/** Offset 0x068F - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
@@ -523,7 +538,7 @@ typedef struct {
/** Offset 0x0690 - Reserved
**/
UINT8 Reserved26[8];
UINT8 Reserved27[8];
/** Offset 0x0698 - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
@@ -534,7 +549,7 @@ typedef struct {
/** Offset 0x069C - Reserved
**/
UINT8 Reserved27[70];
UINT8 Reserved28[70];
/** Offset 0x06E2 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
@@ -544,7 +559,7 @@ typedef struct {
/** Offset 0x06E3 - Reserved
**/
UINT8 Reserved28[33];
UINT8 Reserved29[33];
/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
@@ -553,7 +568,7 @@ typedef struct {
/** Offset 0x0705 - Reserved
**/
UINT8 Reserved29[2];
UINT8 Reserved30[2];
/** Offset 0x0707 - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
@@ -577,7 +592,7 @@ typedef struct {
/** Offset 0x0715 - Reserved
**/
UINT8 Reserved30[2];
UINT8 Reserved31[2];
/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
@@ -588,7 +603,7 @@ typedef struct {
/** Offset 0x0718 - Reserved
**/
UINT8 Reserved31[2];
UINT8 Reserved32[2];
/** Offset 0x071A - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
@@ -604,7 +619,7 @@ typedef struct {
/** Offset 0x0737 - Reserved
**/
UINT8 Reserved32[56];
UINT8 Reserved33[56];
/** Offset 0x076F - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
@@ -618,7 +633,7 @@ typedef struct {
/** Offset 0x07A7 - Reserved
**/
UINT8 Reserved33[196];
UINT8 Reserved34[196];
/** Offset 0x086B - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
@@ -633,7 +648,7 @@ typedef struct {
/** Offset 0x0888 - Reserved
**/
UINT8 Reserved34[5];
UINT8 Reserved35[5];
/** Offset 0x088D - Touch Host Controller Port 1 Assignment
Assign THC Port 1
@@ -643,7 +658,7 @@ typedef struct {
/** Offset 0x088E - Reserved
**/
UINT8 Reserved35[91];
UINT8 Reserved36[91];
/** Offset 0x08E9 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
@@ -659,7 +674,7 @@ typedef struct {
/** Offset 0x0921 - Reserved
**/
UINT8 Reserved36[28];
UINT8 Reserved37[28];
/** Offset 0x093D - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
@@ -668,7 +683,17 @@ typedef struct {
/** Offset 0x0959 - Reserved
**/
UINT8 Reserved37[132];
UINT8 Reserved38[104];
/** Offset 0x09C1 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 PcieComplianceTestMode;
/** Offset 0x09C2 - Reserved
**/
UINT8 Reserved39[27];
/** Offset 0x09DD - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
@@ -678,7 +703,7 @@ typedef struct {
/** Offset 0x09DE - Reserved
**/
UINT8 Reserved38[50];
UINT8 Reserved40[50];
/** Offset 0x0A10 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
@@ -692,7 +717,7 @@ typedef struct {
/** Offset 0x0A28 - Reserved
**/
UINT8 Reserved39[62];
UINT8 Reserved41[62];
/** Offset 0x0A66 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
@@ -706,7 +731,7 @@ typedef struct {
/** Offset 0x0A80 - Reserved
**/
UINT8 Reserved40[16];
UINT8 Reserved42[16];
/** Offset 0x0A90 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
@@ -726,7 +751,7 @@ typedef struct {
/** Offset 0x0A92 - Reserved
**/
UINT8 Reserved41;
UINT8 Reserved43;
/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
@@ -737,7 +762,7 @@ typedef struct {
/** Offset 0x0A94 - Reserved
**/
UINT8 Reserved42[93];
UINT8 Reserved44[93];
/** Offset 0x0AF1 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
@@ -749,7 +774,17 @@ typedef struct {
/** Offset 0x0AF2 - Reserved
**/
UINT8 Reserved43[318];
UINT8 Reserved45[211];
/** Offset 0x0BC5 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 CpuPcieComplianceTestMode;
/** Offset 0x0BC6 - Reserved
**/
UINT8 Reserved46[106];
/** Offset 0x0C30 - RpPtmBytes
**/
@@ -757,7 +792,7 @@ typedef struct {
/** Offset 0x0C34 - Reserved
**/
UINT8 Reserved44[95];
UINT8 Reserved47[95];
/** Offset 0x0C93 - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
@@ -767,7 +802,7 @@ typedef struct {
/** Offset 0x0C94 - Reserved
**/
UINT8 Reserved45;
UINT8 Reserved48;
/** Offset 0x0C95 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
@@ -785,7 +820,7 @@ typedef struct {
/** Offset 0x0C96 - Reserved
**/
UINT8 Reserved46[24];
UINT8 Reserved49[24];
/** Offset 0x0CAE - Enable or Disable HWP
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
@@ -796,7 +831,7 @@ typedef struct {
/** Offset 0x0CAF - Reserved
**/
UINT8 Reserved47[8];
UINT8 Reserved50[8];
/** Offset 0x0CB7 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
@@ -808,7 +843,7 @@ typedef struct {
/** Offset 0x0CB8 - Reserved
**/
UINT8 Reserved48[34];
UINT8 Reserved51[34];
/** Offset 0x0CDA - Enable or Disable CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
@@ -818,7 +853,17 @@ typedef struct {
/** Offset 0x0CDB - Reserved
**/
UINT8 Reserved49[196];
UINT8 Reserved52[157];
/** Offset 0x0D78 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;<b> 1: Enable</b>
$EN_DIS
**/
UINT8 EnableFastMsrHwpReq;
/** Offset 0x0D79 - Reserved
**/
UINT8 Reserved53[38];
/** Offset 0x0D9F - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
@@ -840,7 +885,7 @@ typedef struct {
/** Offset 0x0DA2 - Reserved
**/
UINT8 Reserved50[2];
UINT8 Reserved54[2];
/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
@@ -854,7 +899,7 @@ typedef struct {
/** Offset 0x0E14 - Reserved
**/
UINT8 Reserved51[313];
UINT8 Reserved55[313];
/** Offset 0x0F4D - LpmStateEnableMask
**/
@@ -862,7 +907,7 @@ typedef struct {
/** Offset 0x0F4E - Reserved
**/
UINT8 Reserved52[122];
UINT8 Reserved56[122];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration