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updated for v2

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2003-11-09 23:26:56 +00:00
parent 33ddaac6fd
commit 2f726c3e83
2 changed files with 15 additions and 13 deletions
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16
src/cpu/ppc/mpc74xx/Config.lb
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@ -1,7 +1,21 @@
## ##
## CPU initialization ## CPU initialization
## ##
initinclude "EARLY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc uses _RAMBASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
##
## Use cache ram for initial setup
##
default USE_DCACHE_RAM=1
## Set dcache ram above linuxbios image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
object clock.o object clock.o
initobject clock.o

12
src/cpu/ppc/mpc74xx/mpc74xx.inc
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@ -89,13 +89,6 @@
mtsr 15, r0 mtsr 15, r0
isync isync
/*
* Initialize northbridge. This has to happen early because it
* resets memory. Memory is on at this point, albeit with
* pessimistic settings. We reconfigure later using I2C.
*/
bl bsp_init_northbridge
/* /*
* Set up DBATs * Set up DBATs
* *
@ -183,8 +176,3 @@ tlblp:
ori r2, r2, HID0_ICE | HID0_ICFI ori r2, r2, HID0_ICE | HID0_ICFI
isync isync
mtspr HID0, r2 mtspr HID0, r2
/*
* Must branch to start_payload once CPU initialization is completed
*/
b start_payload