sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/hatch/var/jinlon: Update DPTF parameters

Browse Source 
The change applies the DPTF parameters received from the thermal team.

1. Set PL1 Min to 3W
2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec
3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points
   for tablet mode.
4. Update trigger points of CPU/TSR0/TSR1

BUG=b:154564062, b:154290855
BRANCH=hatch
TEST=build and verified by thermal team.

Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2020-04-21 17:48:10 +08:00 committed by Tim Wawrzynczak
parent 2f58a007a7
commit 2f7f0c62fd
2 changed files with 15 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */ /* This file is part of the coreboot project. */
#define DPTF_CPU_PASSIVE 70 #define DPTF_CPU_PASSIVE 77
#define DPTF_CPU_CRITICAL 105 #define DPTF_CPU_CRITICAL 105
#define DPTF_CPU_ACTIVE_AC0 70 #define DPTF_CPU_ACTIVE_AC0 70
#define DPTF_CPU_ACTIVE_AC1 65 #define DPTF_CPU_ACTIVE_AC1 65
@ -11,13 +11,17 @@
#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
#define DPTF_TSR0_PASSIVE 62 #define DPTF_TSR0_PASSIVE 58
#define DPTF_TSR0_CRITICAL 105 #define DPTF_TSR0_CRITICAL 105
#define DPTF_TSR0_TABLET_PASSIVE 58
#define DPTF_TSR0_TABLET_CRITICAL 105
#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
#define DPTF_TSR1_PASSIVE 54 #define DPTF_TSR1_PASSIVE 57
#define DPTF_TSR1_CRITICAL 105 #define DPTF_TSR1_CRITICAL 86
#define DPTF_TSR1_TABLET_PASSIVE 49
#define DPTF_TSR1_TABLET_CRITICAL 86
#define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_CHARGER
@ -31,13 +35,13 @@ Name (CHPS, Package () {
Name (DTRT, Package () { Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 300, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR0) */ /* CPU Throttle Effect on Ambient (TSR1) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },
/* Charger Throttle Effect on Charger (TSR1) */ /* Charger Throttle Effect on Charger (TSR0) */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 300, 0, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()
@ -45,7 +49,7 @@ Name (MPPC, Package ()
0x2, /* Revision */ 0x2, /* Revision */
Package () { /* Power Limit 1 */ Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
12000, /* PowerLimitMinimum */ 3000, /* PowerLimitMinimum */
15000, /* PowerLimitMaximum */ 15000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMinimum */
32000, /* TimeWindowMaximum */ 32000, /* TimeWindowMaximum */

1
src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h
View File

@ -5,5 +5,6 @@
#define VARIANT_EC_H #define VARIANT_EC_H
#include <baseboard/ec.h> #include <baseboard/ec.h>
#define EC_ENABLE_MULTIPLE_DPTF_PROFILES
#endif #endif