armv7: import new cache maintenance API from coreboot
This imports the new cache maintenance API from coreboot at
commit bba8090. This is a BSD-licensed implementation which
exposes cache maintenance opertaions necessary for payloads
for things such as DMA transfers.
Change-Id: I554676db89517bebc6edae4f7ab7e5882e6f986d
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2974
Tested-by: build bot (Jenkins)
This commit is contained in:
David Hendricks
committed by
Stefan Reinauer
Stefan Reinauer
parent
bc073f4a54
commit
2fba5e27d4
231
payloads/libpayload/include/armv7/arch/cache.h
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231
payloads/libpayload/include/armv7/arch/cache.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef ARMV7_CACHE_H
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#define ARMV7_CACHE_H
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/* SCTLR bits */
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#define SCTLR_M (1 << 0) /* MMU enable */
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#define SCTLR_A (1 << 1) /* Alignment check enable */
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#define SCTLR_C (1 << 2) /* Data/unified cache enable */
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/* Bits 4:3 are reserved */
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#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
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/* Bit 6 is reserved */
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#define SCTLR_B (1 << 7) /* Endianness */
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/* Bits 9:8 */
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#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
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#define SCTLR_Z (1 << 11) /* Branch prediction enable */
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#define SCTLR_I (1 << 12) /* Instruction cache enable */
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#define SCTLR_V (1 << 13) /* Low/high exception vectors */
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#define SCTLR_RR (1 << 14) /* Round Robin select */
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/* Bits 16:15 are reserved */
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#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
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/* Bit 18 is reserved */
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/* Bits 20:19 reserved virtualization not supported */
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#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
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#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
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implies PL1 XN */
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#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
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#define SCTLR_U (1 << 22) /* Unaligned access behavior */
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#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
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#define SCTLR_EE (1 << 25) /* Exception endianness */
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/* Bit 26 is reserved */
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#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
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#define SCTLR_TRE (1 << 28) /* TEX remap enable */
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#define SCTLR_AFE (1 << 29) /* Access flag enable */
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#define SCTLR_TE (1 << 30) /* Thumb exception enable */
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/* Bit 31 is reserved */
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/*
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* Sync primitives
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*/
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/* data memory barrier */
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static inline void dmb(void)
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{
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asm volatile ("dmb" : : : "memory");
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}
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/* data sync barrier */
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static inline void dsb(void)
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{
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asm volatile ("dsb" : : : "memory");
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}
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/* instruction sync barrier */
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static inline void isb(void)
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{
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asm volatile ("isb" : : : "memory");
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}
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/*
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* Low-level TLB maintenance operations
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*/
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/* invalidate entire data TLB */
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static inline void dtlbiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
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}
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/* invalidate entire instruction TLB */
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static inline void itlbiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
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}
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/* invalidate entire unified TLB */
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static inline void tlbiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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}
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/*
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* Low-level cache maintenance operations
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*/
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/* branch predictor invalidate all */
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static inline void bpiall(void)
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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}
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/* data cache clean and invalidate by MVA to PoC */
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static inline void dccimvac(unsigned long mva)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
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}
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/* data cache invalidate by set/way */
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static inline void dccisw(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
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}
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/* data cache invalidate by set/way */
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static inline void dcisw(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val));
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}
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/* data cache clean by MVA to PoC */
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static inline void dccmvac(unsigned long mva)
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{
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asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva));
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}
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/* data cache invalidate by MVA to PoC */
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static inline void dcimvac(unsigned long mva)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
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}
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/* instruction cache invalidate all by PoU */
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static inline void iciallu(void)
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
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}
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/*
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* Cache co-processor (CP15) access functions
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*/
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/* read cache level ID register (CLIDR) */
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static inline uint32_t read_clidr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
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return val;
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}
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/* read cache size ID register register (CCSIDR) */
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static inline uint32_t read_ccsidr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
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return val;
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}
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/* read cache size selection register (CSSELR) */
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static inline uint32_t read_csselr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val));
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return val;
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}
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/* write to cache size selection register (CSSELR) */
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static inline void write_csselr(uint32_t val)
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{
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/*
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* Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
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* Bit 0 - 0 = data or unified cache, 1 = instruction cache
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*/
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val));
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isb(); /* ISB to sync the change to CCSIDR */
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}
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/* read system control register (SCTLR) */
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static inline unsigned int read_sctlr(void)
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{
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unsigned int val;
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asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc");
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return val;
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}
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/* write system control register (SCTLR) */
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static inline void write_sctlr(unsigned int val)
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{
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asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
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isb();
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}
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/*
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* Cache maintenance API
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*/
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/* invalidate all TLBs */
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void tlb_invalidate_all(void);
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/* clean and invalidate entire dcache on current level (given by CCSELR) */
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void dcache_clean_invalidate_all(void);
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/* invalidate entire dcache on current level (given by CCSELR) */
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void dcache_invalidate_all(void);
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/* invalidate and clean dcache by machine virtual address to PoC */
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void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
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/* invalidate entire icache on current level (given by CSSELR) */
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void icache_invalidate_all(void);
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/* MMU setup by machine virtual address */
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void mmu_setup_by_mva(unsigned long start, unsigned long size);
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#endif /* ARMV7_CACHE_H */
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