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i945 northbridge update

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- lots of PCIe updates
- various bug fixes to early init
- some fixes for typos and warnings
- initial support for PCIe x16
- some minor fixes to memory init code
- some subsystem vendor id patches, to be consistent with ICH7

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-03-11 16:20:39 +00:00
committed by Stefan Reinauer
parent d229677b61
commit 30140a59f7
7 changed files with 373 additions and 51 deletions
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11
src/northbridge/intel/i945/raminit.c
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@@ -2160,8 +2160,10 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
reg32 = MCHBAR32(DCC);
#if CHANNEL_XOR_RANDOMIZATION
reg32 &= ~(1 << 10);
#endif
reg32 |= (1 << 9);
#else
reg32 &= ~(1 << 9);
#endif
MCHBAR32(DCC) = reg32;
}
@@ -2242,7 +2244,12 @@ static void sdram_power_management(struct sys_info *sysinfo)
}
MCHBAR16(CPCTL) = reg16;
#if 0
/* This is set later in the game */
if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
#else
if (i945_silicon_revision() != 0) {
#endif
switch (sysinfo->fsb_frequency) {
case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
@@ -2306,7 +2313,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
/* stepping 0 and 1 */
MCHBAR32(FSBPMC4) &= ~(1 << 4);
} else {
MCHBAR32(FSBPMC4) &= ~(1 << 4);
MCHBAR32(FSBPMC4) |= (1 << 4);
}
reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);