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cpu/intel/socket_mPGA478MN: Add socket P

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This mobile CPU socket supports model_6fx and model_1067x.

Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17154
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Arthur Heymans
2016-10-27 00:34:18 +02:00
committed by Martin Roth
parent be91398353
commit 306521b82e
4 changed files with 34 additions and 0 deletions
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1
src/cpu/intel/Kconfig
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@@ -31,6 +31,7 @@ source src/cpu/intel/socket_FCBGA559/Kconfig
source src/cpu/intel/socket_mFCBGA479/Kconfig
source src/cpu/intel/socket_mFCPGA478/Kconfig
source src/cpu/intel/socket_mPGA478/Kconfig
source src/cpu/intel/socket_mPGA478MN/Kconfig
source src/cpu/intel/socket_mPGA479M/Kconfig
source src/cpu/intel/socket_mPGA603/Kconfig
source src/cpu/intel/socket_mPGA604/Kconfig

1
src/cpu/intel/Makefile.inc
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@@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604

18
src/cpu/intel/socket_mPGA478MN/Kconfig Normal file
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@@ -0,0 +1,18 @@
config CPU_INTEL_SOCKET_MPGA478MN
bool
select CPU_INTEL_MODEL_1067X
select CPU_INTEL_MODEL_6FX
select MMX
select SSE
if CPU_INTEL_SOCKET_MPGA478MN
config DCACHE_RAM_BASE
hex
default 0xffaf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
endif

14
src/cpu/intel/socket_mPGA478MN/Makefile.inc Normal file
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@@ -0,0 +1,14 @@
subdirs-y += ../model_6fx
subdirs-y += ../model_1067x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
romstage-y += ../car/romstage.c