mb/hp/snb_ivb_desktops: Make baseboard more generic
In preparation to merging all the other HP sandy/ivy desktops in here as variants. Move hda_verb.c, early_init.c, gma-mainboard.ads and data.vbt into variant directories. Kconfig: Move options not common to the others under the variants instead. devicetree: Move XHCI to variant overridetrees (8200 gen has no USB 3) board_info.txt: Make it more generic. It seems to be copied from 8200 SFF and inaccurate to Z220 anyway. TEST: BUILD_TIMELESS=1 & Don't include .config in ROM image. CMT and SFF ROMs are (SHA1) same as before. Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
This commit is contained in:
committed by
Felix Held
parent
99bf23c9e7
commit
309534183f
@@ -2,8 +2,6 @@
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config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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def_bool n
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def_bool n
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select BOARD_ROMSIZE_KB_16384
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select GFX_GMA_ANALOG_I2C_HDMI_B
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_CMOS_DEFAULT
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@@ -16,15 +14,20 @@ config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select MEMORY_MAPPED_TPM
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select MEMORY_MAPPED_TPM
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_NUVOTON_NPCD378
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select SUPERIO_NUVOTON_NPCD378
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select USE_NATIVE_RAMINIT
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select USE_NATIVE_RAMINIT
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config BOARD_HP_Z220_CMT_WORKSTATION
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config BOARD_HP_Z220_CMT_WORKSTATION
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select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select BOARD_ROMSIZE_KB_16384
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select GFX_GMA_ANALOG_I2C_HDMI_B
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select SOUTHBRIDGE_INTEL_BD82X6X
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config BOARD_HP_Z220_SFF_WORKSTATION
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config BOARD_HP_Z220_SFF_WORKSTATION
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select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select BOARD_ROMSIZE_KB_16384
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select GFX_GMA_ANALOG_I2C_HDMI_B
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select SOUTHBRIDGE_INTEL_BD82X6X
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if BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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if BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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@@ -54,7 +57,7 @@ config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config INTEL_GMA_VBT_FILE
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config INTEL_GMA_VBT_FILE
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default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
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default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/data.vbt"
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config DRAM_RESET_GATE_GPIO
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config DRAM_RESET_GATE_GPIO
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int
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int
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@@ -2,6 +2,7 @@
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bootblock-y += variants/$(VARIANT_DIR)/gpio.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio.c
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romstage-y += variants/$(VARIANT_DIR)/gpio.c
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romstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
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bootblock-y += early_init.c
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bootblock-y += variants/$(VARIANT_DIR)/early_init.c
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romstage-y += early_init.c
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romstage-y += variants/$(VARIANT_DIR)/early_init.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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@@ -1,7 +1,5 @@
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Category: desktop
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Category: desktop
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Board URL: https://support.hp.com/de-de/product/HP-Compaq-8200-Elite-Small-Form-Factor-PC/5037931
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ROM package: SOIC-8 or SOIC-16
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ROM IC: MX25L6405
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ROM package: SOIC-8
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ROM socketed: no
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ROM socketed: no
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Flashrom support: yes
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Flashrom support: yes
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Release year: 2013
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Release year: 2011-2012
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@@ -9,8 +9,6 @@ chip northbridge/intel/sandybridge
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register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
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register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
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device domain 0 on
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device domain 0 on
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subsystemid 0x103c 0x1791 inherit
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device ref host_bridge on end
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device ref host_bridge on end
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device ref peg10 on end
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device ref peg10 on end
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device ref igd on end
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device ref igd on end
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@@ -25,11 +23,7 @@ chip northbridge/intel/sandybridge
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "spi_lvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_switchable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x0000000f"
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device ref xhci on end
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device ref mei1 on end
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device ref mei1 on end
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device ref mei2 off end
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device ref mei2 off end
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device ref me_ide_r off end
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device ref me_ide_r off end
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@@ -6,7 +6,11 @@ chip northbridge/intel/sandybridge
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device ref peg60 on end
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device ref peg60 on end
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chip southbridge/intel/bd82x6x
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chip southbridge/intel/bd82x6x
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register "sata_port_map" = "0x3f"
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register "sata_port_map" = "0x3f"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_switchable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x0000000f"
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device ref xhci on end
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device ref pcie_rp2 on end
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device ref pcie_rp2 on end
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device ref pcie_rp3 on end
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device ref pcie_rp3 on end
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device ref pcie_rp4 on end
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device ref pcie_rp4 on end
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Binary file not shown.
@@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <superio/nuvoton/npcd378/npcd378.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 0, 0 },
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{ 1, 0, 0 },
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{ 1, 0, 0 },
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{ 1, 0, 0 },
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{ 1, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 1, 5 },
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{ 1, 0, 5 },
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{ 1, 0, 5 },
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{ 1, 0, 5 },
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{ 1, 0, 7 },
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{ 1, 0, 7 },
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};
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void bootblock_mainboard_early_init(void)
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{
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if (CONFIG(CONSOLE_SERIAL))
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@@ -0,0 +1,17 @@
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(DP2,
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HDMI2,
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Analog,
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others => Disabled);
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end GMA.Mainboard;
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@@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x10ec0221, /* Codec Vendor / Device ID: Realtek */
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0x103c1791, /* Subsystem ID */
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11, /* Number of 4 dword sets */
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AZALIA_SUBVENDOR(0, 0x103c1791),
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AZALIA_PIN_CFG(0, 0x12, 0x403c0000),
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AZALIA_PIN_CFG(0, 0x14, 0x01014020),
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AZALIA_PIN_CFG(0, 0x17, 0x90170110),
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AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x1a, 0x02a11030),
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AZALIA_PIN_CFG(0, 0x1b, 0x0181303f),
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AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
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AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
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AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
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0x80862806, /* Codec Vendor / Device ID: Intel */
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0x103c1791, /* Subsystem ID */
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4, /* Number of 4 dword sets */
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AZALIA_SUBVENDOR(3, 0x103c1791),
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AZALIA_PIN_CFG(3, 0x05, 0x58560010),
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AZALIA_PIN_CFG(3, 0x06, 0x18560020),
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AZALIA_PIN_CFG(3, 0x07, 0x58560030),
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};
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const u32 pc_beep_verbs[0] = {};
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AZALIA_ARRAY_SIZES;
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@@ -6,7 +6,11 @@ chip northbridge/intel/sandybridge
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chip southbridge/intel/bd82x6x
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chip southbridge/intel/bd82x6x
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register "sata_port_map" = "0xf"
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register "sata_port_map" = "0xf"
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device ref pcie_rp5 on end # dummy setting
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_switchable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x0000000f"
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device ref xhci on end
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end
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end
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end
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end
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end
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end
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