mb/hp/snb_ivb_desktops: Make baseboard more generic

In preparation to merging all the other HP sandy/ivy desktops in here
as variants.

Move hda_verb.c, early_init.c, gma-mainboard.ads and data.vbt into
variant directories.

Kconfig:
Move options not common to the others under the variants instead.

devicetree:
Move XHCI to variant overridetrees (8200 gen has no USB 3)

board_info.txt:
Make it more generic. It seems to be copied from 8200 SFF and
inaccurate to Z220 anyway.

TEST: BUILD_TIMELESS=1 & Don't include .config in ROM image. CMT and
SFF ROMs are (SHA1) same as before.

Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
This commit is contained in:
Riku Viitanen
2024-02-14 01:18:45 +02:00
committed by Felix Held
parent 99bf23c9e7
commit 309534183f
14 changed files with 102 additions and 18 deletions

View File

@@ -2,8 +2,6 @@
config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
def_bool n
select BOARD_ROMSIZE_KB_16384
select GFX_GMA_ANALOG_I2C_HDMI_B
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
@@ -16,15 +14,20 @@ config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
select MEMORY_MAPPED_TPM
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select SUPERIO_NUVOTON_NPCD378
select USE_NATIVE_RAMINIT
config BOARD_HP_Z220_CMT_WORKSTATION
select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
select BOARD_ROMSIZE_KB_16384
select GFX_GMA_ANALOG_I2C_HDMI_B
select SOUTHBRIDGE_INTEL_BD82X6X
config BOARD_HP_Z220_SFF_WORKSTATION
select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
select BOARD_ROMSIZE_KB_16384
select GFX_GMA_ANALOG_I2C_HDMI_B
select SOUTHBRIDGE_INTEL_BD82X6X
if BOARD_HP_SNB_IVB_DESKTOPS_COMMON
@@ -54,7 +57,7 @@ config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config INTEL_GMA_VBT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/data.vbt"
config DRAM_RESET_GATE_GPIO
int

View File

@@ -2,6 +2,7 @@
bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
bootblock-y += variants/$(VARIANT_DIR)/early_init.c
romstage-y += variants/$(VARIANT_DIR)/early_init.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

View File

@@ -1,7 +1,5 @@
Category: desktop
Board URL: https://support.hp.com/de-de/product/HP-Compaq-8200-Elite-Small-Form-Factor-PC/5037931
ROM IC: MX25L6405
ROM package: SOIC-8
ROM package: SOIC-8 or SOIC-16
ROM socketed: no
Flashrom support: yes
Release year: 2013
Release year: 2011-2012

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@@ -9,8 +9,6 @@ chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
device domain 0 on
subsystemid 0x103c 0x1791 inherit
device ref host_bridge on end
device ref peg10 on end
device ref igd on end
@@ -25,11 +23,7 @@ chip northbridge/intel/sandybridge
register "sata_interface_speed_support" = "0x3"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x0000000f"
device ref xhci on end
device ref mei1 on end
device ref mei2 off end
device ref me_ide_r off end

View File

@@ -6,7 +6,11 @@ chip northbridge/intel/sandybridge
device ref peg60 on end
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x0000000f"
device ref xhci on end
device ref pcie_rp2 on end
device ref pcie_rp3 on end
device ref pcie_rp4 on end

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@@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <superio/nuvoton/npcd378/npcd378.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <southbridge/intel/bd82x6x/pch.h>
#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 },
{ 1, 0, 0 },
{ 1, 0, 0 },
{ 1, 0, 0 },
{ 1, 0, 3 },
{ 1, 0, 3 },
{ 1, 0, 3 },
{ 1, 0, 3 },
{ 1, 1, 5 },
{ 1, 0, 5 },
{ 1, 0, 5 },
{ 1, 0, 5 },
{ 1, 0, 7 },
{ 1, 0, 7 },
};
void bootblock_mainboard_early_init(void)
{
if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

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@@ -0,0 +1,17 @@
-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(DP2,
HDMI2,
Analog,
others => Disabled);
end GMA.Mainboard;

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@@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0221, /* Codec Vendor / Device ID: Realtek */
0x103c1791, /* Subsystem ID */
11, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x103c1791),
AZALIA_PIN_CFG(0, 0x12, 0x403c0000),
AZALIA_PIN_CFG(0, 0x14, 0x01014020),
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x02a11030),
AZALIA_PIN_CFG(0, 0x1b, 0x0181303f),
AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
0x80862806, /* Codec Vendor / Device ID: Intel */
0x103c1791, /* Subsystem ID */
4, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(3, 0x103c1791),
AZALIA_PIN_CFG(3, 0x05, 0x58560010),
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
AZALIA_PIN_CFG(3, 0x07, 0x58560030),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

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@@ -6,7 +6,11 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0xf"
device ref pcie_rp5 on end # dummy setting
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x0000000f"
device ref xhci on end
end
end
end