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fsp_baytrail: remove register option for TSEG size

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Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.

Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7490
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
This commit is contained in:
Martin Roth
2014-11-16 20:28:57 -07:00
committed by Martin Roth
parent bdfe98f92f
commit 30eda3edd7
4 changed files with 2 additions and 18 deletions
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14
src/soc/intel/fsp_baytrail/chip.h
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@@ -51,20 +51,6 @@ struct soc_intel_fsp_baytrail_config {
#define SATA_MODE_IDE INCREMENT_FOR_DEFAULT(0)
#define SATA_MODE_AHCI INCREMENT_FOR_DEFAULT(1)
/*
* MrcInitTsegSize
* 0x01, "1 MB"
* 0x02, "2 MB"
* 0x04, "4 MB"
* 0x08, "8 MB"
*/
uint16_t PcdMrcInitTsegSize;
#define TSEG_SIZE_DEFAULT UPD_DEFAULT
#define TSEG_SIZE_1_MB INCREMENT_FOR_DEFAULT(1)
#define TSEG_SIZE_2_MB INCREMENT_FOR_DEFAULT(2)
#define TSEG_SIZE_4_MB INCREMENT_FOR_DEFAULT(4)
#define TSEG_SIZE_8_MB INCREMENT_FOR_DEFAULT(8)
/*
* MrcInitMmioSize
* 0x400, "1.0 GB"s