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haswell: Misc updates from 1.6.1 ref code

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These programming sequences were changed in the latest code.

Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65612
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Duncan Laurie
2013-08-12 13:51:22 -07:00
committed by Patrick Georgi
parent 4fb3a61fc6
commit 3106d0ffce
2 changed files with 5 additions and 17 deletions
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3
src/southbridge/intel/lynxpoint/pcie.c
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@@ -649,9 +649,6 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74);
/* Set undocumented bits in MPC2 register. */
pcie_update_cfg(dev, 0xd4, ~0, (1 << 12) | (1 << 6));
/* Set Invalid Recieve Range Check Enable in MPC register. */
pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));