soc/intel/xeon_sp: Use ACPI common flags in SRAT generation

Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED
and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common
codes.

TEST=intel/archercity CRB

Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Shuo Liu
2022-07-05 22:56:28 +08:00
committed by Felix Held
parent 08f1f05bf6
commit 3108ba5a07
5 changed files with 7 additions and 18 deletions

View File

@ -60,11 +60,6 @@ are permitted provided that the following conditions are met:
MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
)
/* ACPI SRAT Memory Flags */
#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
#define MEM_TYPE_RESERVED (1 << 8)
#define MEM_ADDR_64MB_SHIFT_BITS 26

View File

@ -45,11 +45,6 @@ are permitted provided that the following conditions are met:
#define MEMTYPE_2LM_MASK (1 << 1)
#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
/* ACPI SRAT Memory Flags */
#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
#define MEM_TYPE_RESERVED (1 << 8)
#define MEM_ADDR_64MB_SHIFT_BITS 26
@ -68,4 +63,4 @@ are permitted provided that the following conditions are met:
// #define MAX_SAD_RULES 16
// #define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
#endif
#endif

View File

@ -46,11 +46,6 @@ are permitted provided that the following conditions are met:
MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
)
/* ACPI SRAT Memory Flags */
#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
#define MEM_TYPE_RESERVED (1 << 8)
#define MEM_ADDR_64MB_SHIFT_BITS 26