soc/intel/xeon_sp: Use ACPI common flags in SRAT generation
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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@ -60,11 +60,6 @@ are permitted provided that the following conditions are met:
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MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
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)
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/* ACPI SRAT Memory Flags */
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#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
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#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
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#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
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#define MEM_TYPE_RESERVED (1 << 8)
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#define MEM_ADDR_64MB_SHIFT_BITS 26
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@ -45,11 +45,6 @@ are permitted provided that the following conditions are met:
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#define MEMTYPE_2LM_MASK (1 << 1)
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#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
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/* ACPI SRAT Memory Flags */
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#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
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#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
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#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
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#define MEM_TYPE_RESERVED (1 << 8)
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#define MEM_ADDR_64MB_SHIFT_BITS 26
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@ -68,4 +63,4 @@ are permitted provided that the following conditions are met:
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// #define MAX_SAD_RULES 16
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// #define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
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#endif
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#endif
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@ -46,11 +46,6 @@ are permitted provided that the following conditions are met:
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MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
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)
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/* ACPI SRAT Memory Flags */
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#define SRAT_ACPI_MEMORY_ENABLED (1 << 0)
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#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1)
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#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2)
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#define MEM_TYPE_RESERVED (1 << 8)
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#define MEM_ADDR_64MB_SHIFT_BITS 26
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