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soc/intel: deduplicate ACPI timer emulation

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The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.

APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.

Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.

Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner
2020-10-01 22:28:03 +02:00
parent 72e49cef80
commit 310c7637da
13 changed files with 34 additions and 174 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/soc/intel/apollolake/pmutil.c
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@ -178,24 +178,6 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
return prev_sleep_state;
}
void enable_pm_timer_emulation(void)
{
msr_t msr;
if (!CONFIG_CPU_XTAL_HZ)
return;
/*
* The derived frequency is calculated as follows:
* (clock * msr[63:32]) >> 32 = target frequency.
* Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
static int rtc_failed(uint32_t gen_pmcon1)
{
return !!(gen_pmcon1 & RPS);