inteltool: Model 0xf2x, ICH5, i865 support.
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM registers on ICH5. Add ICH5 and i865 to the supported chips list. Enable the dumping of BAR6 on i865. Sample output: Disabling memory access: $ sudo setpci -s 6.0 0x04.b=0x0 $ sudo ./inteltool -m | head -n 9 Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7 Intel Northbridge: 8086:2570 (i865) Intel Southbridge: 8086:24d0 (ICH5) ============= MCHBAR ============ Access to BAR6 is currently disabled, attempting to enable. Enabled successfully. BAR6 = 0xfecf0000 (MEM) Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
committed by
Uwe Hermann
parent
397ff6815f
commit
312fc96874
@@ -297,6 +297,32 @@ static const io_register_t ich6_pm_registers[] = {
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{ 0x54, 4, "C3_RES (Mobile Only)" },
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};
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static const io_register_t ich5_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" },
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{ 0x02, 2, "PM1_EN" },
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{ 0x04, 4, "PM1_CNT" },
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{ 0x08, 4, "PM1_TMR" },
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{ 0x0c, 4, "RESERVED" },
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{ 0x10, 4, "PROC_CNT" },
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{ 0x14, 3, "RESERVED" },
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{ 0x17, 9, "RESERVED" },
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{ 0x20, 1, "RESERVED" },
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{ 0x28, 4, "GPE0_STS" },
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{ 0x2c, 4, "GPE0_EN" },
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{ 0x30, 4, "SMI_EN" },
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{ 0x34, 4, "SMI_STS" },
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{ 0x38, 2, "ALT_GP_SMI_EN" },
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{ 0x3a, 2, "ALT_GP_SMI_STS" },
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{ 0x3c, 4, "RESERVED" },
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{ 0x40, 1, "MON_SMI" },
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{ 0x42, 2, "RESERVED" },
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{ 0x44, 1, "DEVACT_STS" },
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{ 0x48, 1, "DEVTRAP_EN" },
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{ 0x50, 1, "RESERVED" },
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{ 0x51, 15, "RESERVED" },
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{ 0x60, 16, "RESERVED" },
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};
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static const io_register_t ich4_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" },
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{ 0x02, 2, "PM1_EN" },
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@@ -569,6 +595,11 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
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pm_registers = ich6_pm_registers;
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size = ARRAY_SIZE(ich6_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH5:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = ich5_pm_registers;
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size = ARRAY_SIZE(ich5_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH4:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = ich4_pm_registers;
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@@ -629,4 +660,3 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
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return 0;
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}
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