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ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations

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Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.

Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2020-06-28 16:33:33 +03:00
committed by Nico Huber
parent fb777b5da8
commit 3139c8dc05
34 changed files with 114 additions and 116 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/apollolake/acpi.c
View File

@@ -77,8 +77,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
struct soc_intel_apollolake_config *cfg;
cfg = config_of_soc();
/* Clear out GNVS. */
memset(gnvs, 0, sizeof(*gnvs));
if (CONFIG(CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE);

4
src/soc/intel/apollolake/chip.c
View File

@@ -28,7 +28,6 @@
#include <soc/intel/common/vbt.h>
#include <soc/iomap.h>
#include <soc/itss.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/systemagent.h>
@@ -318,9 +317,6 @@ static void soc_init(void *data)
*/
p2sb_unhide();
/* Allocate ACPI NVS in CBMEM */
cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
} else {

11
src/soc/intel/baytrail/ramstage.c
View File

@@ -2,6 +2,7 @@
#include <arch/cpu.h>
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
@@ -143,15 +144,9 @@ static void s3_save_acpi_wake_source(struct global_nvs *gnvs)
static void s3_resume_prepare(void)
{
struct global_nvs *gnvs;
struct global_nvs *gnvs = acpi_get_gnvs();
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (gnvs == NULL)
return;
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(struct global_nvs));
else
if (gnvs && acpi_is_wakeup_s3())
s3_save_acpi_wake_source(gnvs);
}

5
src/soc/intel/baytrail/southcluster.c
View File

@@ -489,11 +489,6 @@ static void southcluster_inject_dsdt(const struct device *device)
struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);

5
src/soc/intel/braswell/acpi.c
View File

@@ -382,11 +382,6 @@ void southcluster_inject_dsdt(const struct device *device)
struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);

21
src/soc/intel/braswell/ramstage.c
View File

@@ -2,6 +2,7 @@
#include <arch/cpu.h>
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
@@ -135,24 +136,11 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
return 1;
}
static void s3_resume_prepare(void)
{
struct global_nvs *gnvs;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
memset(gnvs, 0, sizeof(struct global_nvs));
}
static void set_board_id(void)
{
struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
printk(BIOS_ERR, "Unable to locate Global NVS\n");
struct global_nvs *gnvs = acpi_get_gnvs();
if (!gnvs)
return;
}
gnvs->bdid = board_id();
}
@@ -165,9 +153,6 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config)
/* Allow for SSE instructions to be executed. */
write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
/* Indicate S3 resume to rest of ramstage. */
s3_resume_prepare();
/* Perform silicon specific init. */
intel_silicon_init();
set_max_freq();

12
src/soc/intel/broadwell/pch/lpc.c
View File

@@ -593,8 +593,6 @@ static void pch_lpc_add_io_resources(struct device *dev)
static void pch_lpc_read_resources(struct device *dev)
{
struct global_nvs *gnvs;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -603,11 +601,6 @@ static void pch_lpc_read_resources(struct device *dev)
/* Add IO resources. */
pch_lpc_add_io_resources(dev);
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
memset(gnvs, 0, sizeof(struct global_nvs));
}
static void southcluster_inject_dsdt(const struct device *device)
@@ -615,11 +608,6 @@ static void southcluster_inject_dsdt(const struct device *device)
struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);

11
src/soc/intel/broadwell/ramstage.c
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
@@ -63,15 +64,9 @@ static void save_acpi_wake_source(struct global_nvs *gnvs)
static void s3_resume_prepare(void)
{
struct global_nvs *gnvs;
struct global_nvs *gnvs = acpi_get_gnvs();
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (gnvs == NULL)
return;
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(struct global_nvs));
else
if (gnvs && acpi_is_wakeup_s3())
save_acpi_wake_source(gnvs);
}

1
src/soc/intel/common/Kconfig.common
View File

@@ -2,6 +2,7 @@ config SOC_INTEL_COMMON
bool
select AZALIA_PLUGIN_SUPPORT
select HAVE_DISPLAY_MTRRS
select ACPI_SOC_NVS
help
common code for Intel SOCs

7
src/soc/intel/common/block/acpi/acpi.c
View File

@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/cpu.h>
#include <arch/ioapic.h>
@@ -7,7 +8,6 @@
#include <bootstate.h>
#include <cbmem.h>
#include <cf9_reset.h>
#include <acpi/acpi_gnvs.h>
#include <console/console.h>
#include <cpu/intel/turbo.h>
#include <cpu/intel/common/common.h>
@@ -244,11 +244,6 @@ void southbridge_inject_dsdt(const struct device *device)
struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);

5
src/soc/intel/denverton_ns/acpi.c
View File

@@ -251,11 +251,6 @@ void southcluster_inject_dsdt(const struct device *device)
struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);

12
src/soc/intel/quark/include/soc/nvs.h Normal file
View File

@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_INTEL_QUARK_NVS_H
#define SOC_INTEL_QUARK_NVS_H
#include <stdint.h>
struct __packed global_nvs {
uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
};
#endif /* SOC_INTEL_QUARK_NVS_H */

5
src/soc/intel/skylake/acpi.c
View File

@@ -545,11 +545,6 @@ void southbridge_inject_dsdt(const struct device *device)
struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
if (gnvs) {
acpi_create_gnvs(gnvs);