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vc/intel/raptorlake: Update header files from 4435_00 to 5045_00

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Update header files for FSP for Raptor Lake refresh platform to
version 5045_00, previous version being 4435_00.

FSPM:
1. Add IgdGsm2Size UPD
2. Comment added for Offset 0x0AB6

FSPS:
1. Add CepEnable UPD
2. Offset size updated for UPD ReservedCpuPostMemProduction
2. Comment added for Offset 0x104C

MemInfoHob:
1. Structure updated

BUG=b:355384183
Kit:https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=815173

Cq-Depend: chrome-internal:7554984
Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Kulkarni, Srinivas 2024-07-25 16:39:32 +05:30 committed by Karthik Ramasubramanian
parent 9ef75eceef
commit 315dba7abb
2 changed files with 17 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h
View File

@ -1091,9 +1091,12 @@ typedef struct {
**/ **/
UINT8 SaVoltageMode; UINT8 SaVoltageMode;
/** Offset 0x029B /** Offset 0x029B - Internal Graphics Data Stolen Memory GSM2
Size of memory preallocated for internal graphics GSM2.
0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB,
11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation
**/ **/
UINT8 Rsvd07; UINT8 IgdGsm2Size;
/** Offset 0x029C - SA/Uncore Voltage Override /** Offset 0x029C - SA/Uncore Voltage Override
The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override
@ -3794,7 +3797,7 @@ typedef struct {
**/ **/
UINT8 CpuPcieRpSlotImplemented[4]; UINT8 CpuPcieRpSlotImplemented[4];
/** Offset 0x0AB6 /** Offset 0x0AB6 - Ppr Run Once
Enable PPR Run Once 0:Disable, <b>1:Enable<b> Enable PPR Run Once 0:Disable, <b>1:Enable<b>
0:Disable, 1:Enable 0:Disable, 1:Enable
**/ **/

15
src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h
View File

@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
@ -1778,11 +1778,17 @@ typedef struct {
**/ **/
UINT32 PsysCriticalThreshold; UINT32 PsysCriticalThreshold;
/** Offset 0x06E0 - ReservedCpuPostMemProduction /** Offset 0x06E0 - CepEnable
Enable or Disable Cep (Current Excursion Protection) Support.
1: Enable, 0: Disable
**/
UINT8 CepEnable[5];
/** Offset 0x06E5 - ReservedCpuPostMemProduction
Reserved for CPU Post-Mem Production Reserved for CPU Post-Mem Production
$EN_DIS $EN_DIS
**/ **/
UINT8 ReservedCpuPostMemProduction[11]; UINT8 ReservedCpuPostMemProduction[6];
/** Offset 0x06EB - Enable Power Optimizer /** Offset 0x06EB - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side. Enable DMI Power Optimizer on PCH side.
@ -4294,7 +4300,8 @@ typedef struct {
**/ **/
UINT32 ThcHidFlags[2]; UINT32 ThcHidFlags[2];
/** Offset 0x104C /** Offset 0x104C - Force LTR Override
Force LTR Override.
**/ **/
UINT8 CpuPcieRpTestForceLtrOverride[4]; UINT8 CpuPcieRpTestForceLtrOverride[4];