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soc/intel/quark: FSP MemoryInit Support

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Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select DISPLAY_HOBS"
   *  Add "select DISPLAY_UPD_DATA"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
    CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  MemoryInit returns 0 (success) and
   *  The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed

Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13447
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Lee Leahy
2016-02-07 14:48:53 -08:00
committed by Stefan Reinauer
parent c285b30b7d
commit 318ef96af3
1 changed files with 14 additions and 0 deletions
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14
src/soc/intel/quark/romstage/romstage.c
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@@ -14,9 +14,12 @@
* GNU General Public License for more details.
*/
#include <arch/early_variables.h>
#include <console/console.h>
#include <fsp/car.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
void car_soc_pre_console_init(void)
@@ -25,3 +28,14 @@ void car_soc_pre_console_init(void)
set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC,
UART_BASE_ADDRESS);
}
static struct chipset_power_state power_state CAR_GLOBAL;
struct chipset_power_state *fill_power_state(void)
{
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
ps->prev_sleep_state = 0;
printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
return ps;
}