treewide: Replace uses of "Nehalem"

The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:

- Hillel:   32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics

This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.

Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/common/fsb.c

@@ -48,7 +48,7 @@ static int get_fsb_tsc(int *fsb, int *ratio)
 			*fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
 			*ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f;
 			break;
-		case 0x25: /* Nehalem BCLK fixed at 133MHz */
+		case 0x25: /* Arrandale BCLK fixed at 133MHz */
 			*fsb = 133;
 			*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
 			break;

src/cpu/intel/model_2065x/acpi.c

@@ -338,5 +338,5 @@ void generate_cpu_entries(struct device *device)
 }
 
 struct chip_operations cpu_intel_model_2065x_ops = {
-	CHIP_NAME("Intel Nehalem CPU")
+	CHIP_NAME("Intel Arrandale CPU")
 };

src/cpu/intel/model_2065x/model_2065x.h

@@ -15,7 +15,7 @@
 #ifndef _CPU_INTEL_MODEL_2065X_H
 #define _CPU_INTEL_MODEL_2065X_H
 
-/* Nehalem bus clock is fixed at 133MHz */
+/* Arrandale bus clock is fixed at 133MHz */
 #define IRONLAKE_BCLK		133
 
 #define MSR_CORE_THREAD_COUNT		0x35