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PCIe: Add L1 Sub-State support.

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Enable L1 Sub-State when both root port and endpoint support it.

[pg: keyed the feature to MMCONF_SUPPORT, otherwise boards
without that capability fail to build.]

Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092
Original-BUG=chrome-os-partner:31424
Original-TEST=Build a image and run on Samus proto boards to check if the
settings are applied correctly. I just only have proto boards and
need someone having EVT boards to confirm the settings.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
Original-Reviewed-on: https://chromium-review.googlesource.com/221436
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kenji Chen
2014-10-04 01:14:44 +08:00
committed by Patrick Georgi
parent 431e51ec2a
commit 31c6e632cf
5 changed files with 200 additions and 0 deletions
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8
src/device/Kconfig
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@@ -271,6 +271,14 @@ config EARLY_PCI_BRIDGE
This option enables static configuration for a single pre-defined
PCI bridge function on bus 0.
config PCIEXP_L1_SUB_STATE
prompt "Enable PCIe ASPM L1 SubState"
bool
depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT
default n
help
Detect and enable ASPM on PCIe links.
if EARLY_PCI_BRIDGE
config EARLY_PCI_BRIDGE_DEVICE