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soc/amd: factor out memmap from root_complex

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Now that the SoC-specific memory map is reported on the domain device
instead of the northbridge device, factor out the
read_soc_memmap_resources function from root_complex.c to new memmap.c
file. For now each SoC still has its own memmap.c file, but the plan is
to eventually have a common implementation that works for all AMD family
17h+ SoCs. For that I'll still need to look closer into the differences
between the FSP and the openSIL integration though.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Felix Held
2024-01-30 18:42:38 +01:00
parent f9fb108610
commit 31ca978c23
15 changed files with 494 additions and 479 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/amd/cezanne/Makefile.mk
View File

@@ -25,6 +25,7 @@ ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += memmap.c
ramstage-y += root_complex.c
ramstage-y += xhci.c

98
src/soc/amd/cezanne/memmap.c Normal file
View File

@@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <device/device.h>
#include <stdint.h>
/*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (86KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (64KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}

96
src/soc/amd/cezanne/root_complex.c
View File

@@ -1,17 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
#include <amdblocks/acpi.h>
#include <amdblocks/alib.h>
#include <amdblocks/data_fabric.h>
#include <amdblocks/ioapic.h>
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/ioapic.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <soc/iomap.h>
@@ -48,96 +42,6 @@ struct dptc_input {
}, \
}
/*
*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (86KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (64KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}
static void root_complex_init(struct device *dev)
{
register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);

1
src/soc/amd/glinda/Makefile.mk
View File

@@ -29,6 +29,7 @@ ramstage-y += cpu.c
ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += mca.c
ramstage-y += memmap.c
ramstage-y += root_complex.c
ramstage-y += xhci.c

98
src/soc/amd/glinda/memmap.c Normal file
View File

@@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <device/device.h>
#include <stdint.h>
/*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (30KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}

96
src/soc/amd/glinda/root_complex.c
View File

@@ -3,17 +3,11 @@
/* TODO: Update for Glinda */
#include <acpi/acpigen.h>
#include <amdblocks/acpi.h>
#include <amdblocks/alib.h>
#include <amdblocks/data_fabric.h>
#include <amdblocks/ioapic.h>
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/ioapic.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <soc/iomap.h>
@@ -63,96 +57,6 @@ struct dptc_input {
}, \
}
/*
*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (30KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}
static void root_complex_init(struct device *dev)
{
register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);

1
src/soc/amd/mendocino/Makefile.mk
View File

@@ -27,6 +27,7 @@ ramstage-y += fch.c
ramstage-y += fsp_misc_data_hob.c
ramstage-y += fsp_s_params.c
ramstage-y += mca.c
ramstage-y += memmap.c
ramstage-y += root_complex.c
ramstage-y += xhci.c
ramstage-y += manifest.c

98
src/soc/amd/mendocino/memmap.c Normal file
View File

@@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <device/device.h>
#include <stdint.h>
/*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (30KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}

96
src/soc/amd/mendocino/root_complex.c
View File

@@ -3,17 +3,11 @@
/* TODO: Check if this is still correct */
#include <acpi/acpigen.h>
#include <amdblocks/acpi.h>
#include <amdblocks/alib.h>
#include <amdblocks/data_fabric.h>
#include <amdblocks/ioapic.h>
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/ioapic.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <fsp/amd_misc_data.h>
@@ -91,96 +85,6 @@ struct dptc_input {
}, \
}
/*
*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (30KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}
static void root_complex_init(struct device *dev)
{
register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);

1
src/soc/amd/phoenix/Makefile.mk
View File

@@ -31,6 +31,7 @@ ramstage-y += fch.c
ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += memmap.c
ramstage-y += root_complex.c
ramstage-y += soc_util.c
ramstage-y += xhci.c

99
src/soc/amd/phoenix/memmap.c Normal file
View File

@@ -0,0 +1,99 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <device/device.h>
#include <stdint.h>
/*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (30KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
if (CONFIG(PLATFORM_USES_FSP2_0))
read_fsp_resources(dev, idx);
}

97
src/soc/amd/phoenix/root_complex.c
View File

@@ -3,17 +3,11 @@
/* TODO: Update for Phoenix */
#include <acpi/acpigen.h>
#include <amdblocks/acpi.h>
#include <amdblocks/alib.h>
#include <amdblocks/data_fabric.h>
#include <amdblocks/ioapic.h>
#include <amdblocks/iomap.h>
#include <amdblocks/memmap.h>
#include <amdblocks/root_complex.h>
#include <arch/ioapic.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <soc/iomap.h>
@@ -63,97 +57,6 @@ struct dptc_input {
}, \
}
/*
*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (30KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (120KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
if (CONFIG(PLATFORM_USES_FSP2_0))
read_fsp_resources(dev, idx);
}
static void root_complex_init(struct device *dev)
{
register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);

1
src/soc/amd/picasso/Makefile.mk
View File

@@ -26,6 +26,7 @@ ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += memmap.c
ramstage-y += pcie_gpp.c
ramstage-y += root_complex.c
ramstage-y += sata.c

96
src/soc/amd/picasso/memmap.c Normal file
View File

@@ -0,0 +1,96 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/memmap.h>
#include <amdblocks/iomap.h>
#include <amdblocks/root_complex.h>
#include <arch/vga.h>
#include <cbmem.h>
#include <device/device.h>
#include <stdint.h>
/*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (86KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (64KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used. */
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}

94
src/soc/amd/picasso/root_complex.c
View File

@@ -1,18 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
#include <amdblocks/acpi.h>
#include <amdblocks/alib.h>
#include <amdblocks/data_fabric.h>
#include <amdblocks/memmap.h>
#include <amdblocks/ioapic.h>
#include <amdblocks/iomap.h>
#include <amdblocks/root_complex.h>
#include <arch/ioapic.h>
#include <arch/vga.h>
#include <assert.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <stdint.h>
@@ -48,93 +41,6 @@ struct dptc_input {
}, \
}, \
}
/*
*
* +--------------------------------+
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* reserved_dram_end +--------------------------------+
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
* | |
* | FSP-M |
* | (FSP_M_SIZE) |
* +--------------------------------+ FSP_M_ADDR
* | romstage |
* | (ROMSTAGE_SIZE) |
* +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
* | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
* | bootblock |
* | (C_ENV_BOOTBLOCK_SIZE) |
* +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
* | Unused hole |
* | (86KiB) |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
* | Preram CBMEM console |
* | (PRERAM_CBMEM_CONSOLE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
* | PSP shared (vboot workbuf) |
* | (PSP_SHAREDMEM_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE
* | APOB (64KiB) |
* +--------------------------------+ PSP_APOB_DRAM_ADDRESS
* | Early BSP stack |
* | (EARLYRAM_BSP_STACK_SIZE) |
* reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
* | DRAM |
* +--------------------------------+ 0x100000
* | Option ROM |
* +--------------------------------+ 0xc0000
* | Legacy VGA |
* +--------------------------------+ 0xa0000
* | DRAM |
* +--------------------------------+ 0x0
*/
void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
{
uint32_t mem_usable = (uintptr_t)cbmem_top();
uintptr_t early_reserved_dram_start, early_reserved_dram_end;
const struct memmap_early_dram *e = memmap_get_early_dram_usage();
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* 0x0 - 0x9ffff */
ram_range(dev, (*idx)++, 0, 0xa0000);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
/* 1MB - bottom of DRAM reserved for early coreboot usage */
ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
/* DRAM reserved for early coreboot usage */
reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
/* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used. */
ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
/* Reserve fixed IOMMU MMIO region */
mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
read_fsp_resources(dev, idx);
}
static void root_complex_init(struct device *dev)
{