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soc/intel/cannonlake: Add SPI flash controller driver

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Add SPI driver code for the SPI flash controller, including both
fast_spi and generic_spi.

Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao
2017-08-16 11:40:03 -07:00
committed by Aaron Durbin
parent 201fa8ffe5
commit 321111774c
6 changed files with 163 additions and 0 deletions
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9
src/soc/intel/cannonlake/Kconfig
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@@ -11,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select HAVE_HARD_RESET
@@ -29,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
@@ -38,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
select SOC_INTEL_COMMON_RESET
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
@@ -78,6 +82,11 @@ config CPU_BCLK_MHZ
int
default 100
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex