sravan/system76-coreboot
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Various cosmetic changes and coding style fixes (trivial).

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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2007-09-24 20:00:32 +00:00
parent 0f86732a5e
commit 322076cdad
1 changed files with 183 additions and 188 deletions
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81
src/mainboard/asus/a8n_e/Config.lb
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@ -39,22 +39,21 @@ else
end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
## Compute the start location and size size of the LinuxBIOS bootloader.
##
default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of linuxBIOS will start in the boot rom
## Compute where this copy of LinuxBIOS will start in the boot ROM.
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## Compute a range of ROM that can be cached to speed up LinuxBIOS
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2. (here 64 Kbyte)
## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte)
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE = (64 * 1024)
@ -107,7 +106,7 @@ if USE_DCACHE_RAM
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
## Build our 16 bit and 32 bit LinuxBIOS entry code.
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@ -126,15 +125,12 @@ mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
## Build our reset vector (this is where LinuxBIOS is entered).
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@ -161,7 +157,7 @@ else
end
##
## Include an id string (For safe flashing)
## Include an ID string (for safe flashing).
##
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds
@ -190,7 +186,7 @@ end
###
### This is the early phase of linuxBIOS startup
### This is the early phase of LinuxBIOS startup.
### Things are delicate and we test to see if we should
### failover to another image.
###
@ -230,52 +226,52 @@ if CONFIG_CHIP_NAME
config chip.h
end
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_939
device apic 0 on end
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
chip cpu/amd/socket_939 # Socket 939 CPU
device apic 0 on end # APIC
end
end
device pci_domain 0 on
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # northbridge
device pci 18.0 on # Northbridge
# Devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804
chip southbridge/nvidia/ck804 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/ite/it8712f
chip superio/ite/it8712f # Super I/O
device pnp 2e.0 off # Floppy
io 0x60 = 0x03f0
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Com1
io 0x60 = 0x03f8
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 off # Com2
io 0x60 = 0x02f8
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel Port
io 0x60 = 0x0378
device pnp 2e.3 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0290
device pnp 2e.4 on # Environment controller
io 0x60 = 0x290
io 0x62 = 0x0000
irq 0x70 = 0x00
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 0x01
irq 0x71 = 0x02
device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x71 = 2
end
device pnp 2e.6 on # Mouse
irq 0x70 = 0x0c
irq 0x71 = 0x02
device pnp 2e.6 on # PS/2 mouse
irq 0x70 = 12
irq 0x71 = 2
end
device pnp 2e.7 on # GPIO config
# Set GPIO 1 & 2
@ -322,11 +318,11 @@ chip northbridge/amd/amdk8/root_complex
# chip drivers/generic/generic #dimm 1-1-1
# device i2c 57 on end
# end
end # SM
end
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 off end # ACI
device pci 4.1 off end # MCI
device pci 4.0 off end # Onboard audio (ACI)
device pci 4.1 off end # Onboard modem (MCI)
device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0
@ -343,11 +339,10 @@ chip northbridge/amd/amdk8/root_complex
# register "mac_eeprom_smbus" = "3"
# register "mac_eeprom_addr" = "0x51"
end
end # device pci 18.0
end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # mc0
end # pci_domain
end # root_complex
end
end
end