Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
439
src/soc/intel/braswell/gpio.c
Normal file → Executable file
439
src/soc/intel/braswell/gpio.c
Normal file → Executable file
@@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -17,228 +18,298 @@
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* Foundation, Inc.
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*/
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#include <device/pci.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <soc/gpio.h>
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#include <soc/pmc.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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/* GPIO-to-Pad LUTs */
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static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
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{ 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
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23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
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4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
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2, 5, 9 }; /* [24:26] */
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static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
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{ 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
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34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
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62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
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63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
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48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
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95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
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65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
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79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
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15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
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0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
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31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
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21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
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106, 87, 91, 104, 97, 100 }; /* [96:101] */
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#define GPIO_DEBUG
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static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
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{ 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
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38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
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8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
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28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
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56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
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52, 53, 59, 40 }; /* [40:43] */
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/* gpio map to pad number LUTs */
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/* GPIO bank descriptions */
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static const struct gpio_bank gpncore_bank = {
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.gpio_count = GPNCORE_COUNT,
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.gpio_to_pad = gpncore_gpio_to_pad,
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.legacy_base = GP_LEGACY_BASE_NONE,
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.pad_base = GPNCORE_PAD_BASE,
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.has_wake_en = 0,
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.gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
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.gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
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};
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static const u8 gpncommunity_gpio_to_pad[GP_NORTH_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 15,
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
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26, 27, 30, 31, 32, 33, 34, 35, 36, 37,
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38, 39, 40, 41, 45, 46, 47, 48, 49, 50,
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51, 52, 53, 54, 55, 56, 60, 61, 62, 63,
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64, 65, 66, 67, 68, 69, 70, 71, 72 };
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static const struct gpio_bank gpscore_bank = {
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.gpio_count = GPSCORE_COUNT,
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.gpio_to_pad = gpscore_gpio_to_pad,
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.legacy_base = GPSCORE_LEGACY_BASE,
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.pad_base = GPSCORE_PAD_BASE,
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.has_wake_en = 0,
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.gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START,
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.gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END,
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};
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static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
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30, 31, 32, 33, 34, 35, 45, 46, 47, 48,
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49, 50, 51, 52, 60, 61, 62, 63, 64, 65,
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66, 67, 68, 69, 75, 76, 77, 78, 79, 80,
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81, 82, 83, 84, 85 };
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static const struct gpio_bank gpssus_bank = {
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.gpio_count = GPSSUS_COUNT,
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.gpio_to_pad = gpssus_gpio_to_pad,
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.legacy_base = GPSSUS_LEGACY_BASE,
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.pad_base = GPSSUS_PAD_BASE,
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static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 15, 16,
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17, 18, 19, 20, 21, 22, 30, 31, 32, 33,
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34, 35, 36, 37, 45, 46, 47, 48, 49, 50,
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51, 52, 60, 61, 62, 63, 64, 65, 66, 67,
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75, 76, 77, 78, 79, 80, 81, 82, 90, 91,
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92, 93, 94, 95, 96, 97 };
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static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
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10, 11, 15, 16, 17, 18, 19, 20, 21, 22,
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23, 24, 25, 26 };
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/* GPIO Community descriptions */
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static const struct gpio_bank gpnorth_community = {
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.gpio_count = GP_NORTH_COUNT,
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.gpio_to_pad = gpncommunity_gpio_to_pad ,
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.pad_base = COMMUNITY_GPNORTH_BASE ,
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.has_gpe_en = GPE_CAPABLE ,
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.has_wake_en = 1,
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.gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START,
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.gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END,
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};
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static void setup_gpios(const struct soc_gpio_map *gpios,
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const struct gpio_bank *bank)
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{
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const struct soc_gpio_map *config;
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int gpio = 0;
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u32 reg, pad_conf0;
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u8 set, bit;
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u32 use_sel[4] = {0};
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u32 io_sel[4] = {0};
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u32 gp_lvl[4] = {0};
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u32 tpe[4] = {0};
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u32 tne[4] = {0};
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u32 wake_en[4] = {0};
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if (!gpios)
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return;
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for (config = gpios; config->pad_conf0 != GPIO_LIST_END;
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config++, gpio++) {
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if (gpio > bank->gpio_count)
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break;
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set = gpio >> 5;
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bit = gpio % 32;
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if (bank->legacy_base != GP_LEGACY_BASE_NONE) {
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/* Legacy IO configuration */
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use_sel[set] |= config->use_sel << bit;
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io_sel[set] |= config->io_sel << bit;
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gp_lvl[set] |= config->gp_lvl << bit;
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tpe[set] |= config->tpe << bit;
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tne[set] |= config->tne << bit;
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/* Some banks do not have wake_en ability */
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if (bank->has_wake_en)
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wake_en[set] |= config->wake_en << bit;
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}
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/* Pad configuration registers */
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reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
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/* Add correct func to GPIO pad config */
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pad_conf0 = config->pad_conf0;
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if (config->is_gpio)
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{
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if (gpio >= bank->gpio_f1_range_start &&
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gpio <= bank->gpio_f1_range_end)
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pad_conf0 |= PAD_FUNC1;
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else
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pad_conf0 |= PAD_FUNC0;
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}
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
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reg, pad_conf0, config->pad_conf1, config->pad_val);
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#endif
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write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0);
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write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1);
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write32((u32 *)(reg + PAD_VAL_REG), config->pad_val);
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}
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if (bank->legacy_base != GP_LEGACY_BASE_NONE)
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for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) {
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reg = bank->legacy_base + 0x20 * set;
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG,
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"Write GPIO: Reg(%x) - %x %x %x %x %x\n",
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reg, use_sel[set], io_sel[set], gp_lvl[set],
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tpe[set], tne[set]);
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#endif
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outl(use_sel[set], reg + LEGACY_USE_SEL_REG);
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outl(io_sel[set], reg + LEGACY_IO_SEL_REG);
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outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG);
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outl(tpe[set], reg + LEGACY_TPE_REG);
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outl(tne[set], reg + LEGACY_TNE_REG);
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/* TS registers are WOC */
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outl(0, reg + LEGACY_TS_REG);
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if (bank->has_wake_en)
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outl(wake_en[set], reg + LEGACY_WAKE_EN_REG);
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}
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}
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static void setup_gpio_route(const struct soc_gpio_map *sus,
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const struct soc_gpio_map *core)
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static const struct gpio_bank gpsoutheast_community = {
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.gpio_count = GP_SOUTHEAST_COUNT,
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.gpio_to_pad = gpsecommunity_gpio_to_pad,
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.pad_base = COMMUNITY_GPSOUTHEAST_BASE,
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.has_gpe_en = GPE_CAPABLE_NONE,
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.has_wake_en = 1,
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};
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static const struct gpio_bank gpsouthwest_community = {
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.gpio_count = GP_SOUTHWEST_COUNT,
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.gpio_to_pad = gpswcommunity_gpio_to_pad,
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.pad_base = COMMUNITY_GPSOUTHWEST_BASE,
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.has_gpe_en = GPE_CAPABLE,
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.has_wake_en = 1,
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};
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static const struct gpio_bank gpeast_community = {
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.gpio_count = GP_EAST_COUNT,
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.gpio_to_pad = gpecommunity_gpio_to_pad,
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.pad_base = COMMUNITY_GPEAST_BASE,
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.has_gpe_en = GPE_CAPABLE_NONE,
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.has_wake_en = 1,
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};
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static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
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const struct soc_gpio_map *n_gpios)
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{
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const struct soc_gpio_map *n_config;
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const struct soc_gpio_map *sw_config;
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uint32_t route_reg = 0;
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int i;
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uint32_t int_selection = 0;
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uint32_t alt_gpio_smi = 0;
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uint32_t gpe0a_en = 0;
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int gpio = 0;
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int north_done = 0;
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int south_done = 0;
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for (i = 0; i < 8; i++) {
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/* SMI takes precedence and wake_en implies SCI. */
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if (sus[i].smi) {
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route_reg |= ROUTE_SMI << (2 * i);
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} else if (sus[i].sci) {
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route_reg |= ROUTE_SCI << (2 * i);
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for (sw_config = sw_gpios, n_config = n_gpios;
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(!north_done || !south_done); sw_config++, n_config++, gpio++) {
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/* when north config is done */
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if ((gpio > GP_NORTH_COUNT) ||
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(n_config->pad_conf0 == GPIO_LIST_END))
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north_done = 1;
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/* when sw is done */
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if ((gpio > GP_SOUTHWEST_COUNT) ||
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(sw_config->pad_conf0 == GPIO_LIST_END))
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south_done = 1;
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/* route north gpios */
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if (!north_done) {
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/* Int select from 8 to 15 */
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int_selection = ((n_config->pad_conf0 >> 28) & 0xf);
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if (n_config->gpe == SMI) {
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/*
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* Set the corresponding bits (01) as
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* per the interrupt line
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*/
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route_reg |= (1 << ((int_selection - 8) * 2));
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/* reset the higher bit */
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route_reg &=
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~(1 << ((int_selection - 8) * 2 + 1));
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alt_gpio_smi |= (1 << (int_selection + 8));
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} else if (n_config->gpe == SCI) {
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/*
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* Set the corresponding bits as per the
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* interrupt line
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*/
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route_reg |=
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(1 << (((int_selection - 8) * 2) + 1));
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/* reset the bit */
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route_reg &= ~(1 << ((int_selection - 8) * 2));
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gpe0a_en |= (1 << (int_selection + 8));
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}
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}
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if (core[i].smi) {
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route_reg |= ROUTE_SMI << (2 * (i + 8));
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} else if (core[i].sci) {
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route_reg |= ROUTE_SCI << (2 * (i + 8));
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/* route southwest gpios */
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if (!south_done) {
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/* Int select from 8 to 15 */
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int_selection = ((sw_config->pad_conf0 >> 28) & 0xf);
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if (sw_config->gpe == SMI) {
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/*
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* Set the corresponding bits (10) as
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* per the interrupt line
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*/
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route_reg |= (1 << (int_selection * 2));
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route_reg &= ~(1 << (int_selection * 2 + 1));
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alt_gpio_smi |= (1 << (int_selection + 16));
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} else if (sw_config->gpe == SCI) {
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/*
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* Set the corresponding bits as
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* per the interrupt line
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*/
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route_reg |= (1 << ((int_selection * 2) + 1));
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/* reset the bit */
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route_reg &= ~(1 << (int_selection * 2));
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gpe0a_en |= (1 << (int_selection + 16));
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}
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}
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}
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/* enable gpe bits in GPE0A_EN_REG */
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outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG);
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n",
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route_reg, alt_gpio_smi, gpe0a_en);
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#endif
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/* Save as an smm param */
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southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
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}
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static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
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const struct gpio_bank *bank)
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{
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u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
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u32 val;
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int i;
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/* Write all four DIRQ registers */
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for (i=0; i<4; ++i) {
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val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
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dirq[i * 4 + 1] << 8 | dirq[i * 4];
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write32(reg + i, val);
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static void setup_gpios(const struct soc_gpio_map *gpios,
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const struct gpio_bank *community)
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{
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const struct soc_gpio_map *config;
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int gpio = 0;
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u32 reg, family, internal_pad_num;
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u32 mmio_addr, int_selection;
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u32 gpio_wake0 = 0;
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u32 gpio_wake1 = 0;
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u32 gpio_int_mask = 0;
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if (!gpios)
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return;
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for (config = gpios; config->pad_conf0 != GPIO_LIST_END;
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config++, gpio++) {
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if (gpio > community->gpio_count)
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break;
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/* Pad configuration registers */
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family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO;
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internal_pad_num = community->gpio_to_pad[gpio] %
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MAX_FAMILY_PAD_GPIO_NO;
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/*
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* Calculate the MMIO Address for specific GPIO pin
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* control register pointed by index.
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* REG = (IOBASE + COMMUNITY_BASE + (0X04400)) +
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* (0X400*FAMILY_NUM) + (8 * PAD_NUM)
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*/
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mmio_addr = FAMILY_PAD_REGS_OFF
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+ (FAMILY_PAD_REGS_SIZE * family)
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+ (GPIO_REGS_SIZE * internal_pad_num);
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reg = community->pad_base + mmio_addr;
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/* get int selection value */
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int_selection = ((config->pad_conf0 >> 28) & 0xf);
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/* get int mask register value */
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gpio_int_mask |= (config->int_mask << int_selection);
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/*
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* wake capable programming
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* some communities have 2 wake regs
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*/
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if (gpio > 31)
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gpio_wake1 |= config->wake_mask << (gpio % 32);
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else
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gpio_wake0 |= config->wake_mask << gpio;
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if (!config->skip_config) {
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
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reg + i, val);
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printk(BIOS_DEBUG,
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"Write Pad: Base(%x) - conf0 = %x conf1= %x gpio #- %d pad # = %d\n",
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reg, config->pad_conf0, config->pad_conf1,
|
||||
community->gpio_to_pad[gpio], gpio);
|
||||
#endif
|
||||
/*
|
||||
* write pad configurations to conf0 and conf1 register
|
||||
*/
|
||||
write32((void *)(reg + PAD_CONF0_REG),
|
||||
config->pad_conf0);
|
||||
write32((void *)(reg + PAD_CONF1_REG),
|
||||
config->pad_conf1);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef GPIO_DEBUG
|
||||
printk(BIOS_DEBUG,
|
||||
"gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n",
|
||||
gpio_wake0, gpio_wake1, gpio_int_mask);
|
||||
#endif
|
||||
|
||||
/* Wake */
|
||||
write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0),
|
||||
gpio_wake0);
|
||||
|
||||
/* wake mask config for communities with 2 regs */
|
||||
if (community->gpio_count > 32)
|
||||
write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1),
|
||||
gpio_wake1);
|
||||
|
||||
/* Interrupt */
|
||||
write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK),
|
||||
gpio_int_mask);
|
||||
|
||||
}
|
||||
|
||||
|
||||
void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
|
||||
{
|
||||
if (config) {
|
||||
setup_gpios(config->ncore, &gpncore_bank);
|
||||
setup_gpios(config->score, &gpscore_bank);
|
||||
setup_gpios(config->ssus, &gpssus_bank);
|
||||
setup_gpio_route(config->ssus, config->score);
|
||||
|
||||
if (config->core_dirq)
|
||||
setup_dirqs(*config->core_dirq, &gpscore_bank);
|
||||
if (config->sus_dirq)
|
||||
setup_dirqs(*config->sus_dirq, &gpssus_bank);
|
||||
if (config) {
|
||||
|
||||
/*
|
||||
* Write the default value 0xffffff to the SW
|
||||
* write_access_policy_interrupt_reg to allow the SW interrupt
|
||||
* mask register to be set
|
||||
*/
|
||||
write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108),
|
||||
0xffffffff);
|
||||
|
||||
printk(BIOS_DEBUG, "north\n");
|
||||
setup_gpios(config->north, &gpnorth_community);
|
||||
|
||||
printk(BIOS_DEBUG, "southwest\n");
|
||||
setup_gpios(config->southwest, &gpsouthwest_community);
|
||||
|
||||
printk(BIOS_DEBUG, "southeast\n");
|
||||
setup_gpios(config->southeast, &gpsoutheast_community);
|
||||
|
||||
printk(BIOS_DEBUG, "east\n");
|
||||
setup_gpios(config->east, &gpeast_community);
|
||||
|
||||
printk(BIOS_DEBUG, "Routing SW and N gpios\n");
|
||||
setup_gpio_route(config->southwest, config->north);
|
||||
}
|
||||
|
||||
/* Set on die termination feature with pull up value and
|
||||
/*
|
||||
* Set on die termination feature with pull up value and
|
||||
* drive the pad high for TAP_TDO and TAP_TMS
|
||||
*/
|
||||
if (!enable_xdp_tap) {
|
||||
if (!enable_xdp_tap)
|
||||
printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
|
||||
write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc);
|
||||
write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc);
|
||||
}
|
||||
}
|
||||
|
||||
struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)
|
||||
__attribute__((weak)) struct soc_gpio_config *mainboard_get_gpios(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Default/empty GPIO config\n");
|
||||
return NULL;
|
||||
|
||||
Reference in New Issue
Block a user