sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Braswell: Add Braswell SOC support

Browse Source 
Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
2015-04-20 15:20:28 -07:00
committed by Leroy P Leahy
parent 5fe62efb77
commit 32471729d9
94 changed files with 3688 additions and 5359 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/braswell/sd.c
View File

@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -36,7 +37,10 @@
static void sd_init(device_t dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct soc_intel_braswell_config *config = dev->chip_info;
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
if (config == NULL)
return;
@@ -44,12 +48,12 @@ static void sd_init(device_t dev)
if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
pci_write_config32(dev, CAP_OVERRIDE_LOW,
config->sdcard_cap_low);
config->sdcard_cap_low);
pci_write_config32(dev, CAP_OVERRIDE_HIGH,
config->sdcard_cap_high | USE_CAP_OVERRIDES);
config->sdcard_cap_high | USE_CAP_OVERRIDES);
}
if (config->scc_acpi_mode)
if (config->sd_acpi_mode)
scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD);
}
@@ -58,8 +62,6 @@ static const struct device_operations device_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sd_init,
.enable = NULL,
.scan_bus = NULL,
.ops_pci = &soc_pci_ops,
};