mb/system76/oryp5: Add Oryx Pro 5

Change-Id: I0bbbddbb46c1a4a70146e7384ce1fbc9448c9269
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/system76/oryp5/Kconfig

@@ -0,0 +1,77 @@
+if BOARD_SYSTEM76_ORYP5
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COFFEELAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	string
+	default "system76/oryp5"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "oryp5"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Oryx Pro"
+
+config MAINBOARD_VERSION
+	string
+	default "oryp5"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 12
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/oryp5/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ORYP5
+	bool "oryp5"

src/mainboard/system76/oryp5/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/oryp5/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/oryp5/acpi/gpe.asl

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_B23 SCI
+Method (_L17, 0, Serialized)
+{
+	Debug = Concatenate("GPE _L17: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/oryp5/acpi/mainboard.asl

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x17 /* GPP_B23 */
+#define EC_GPE_SWI 0x26 /* GPP_G6 */
+#define EC_COLOR_KEYBOARD 1
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB)
+{
+	#include "sleep.asl"
+	Scope (PCI0)
+	{
+		#include "backlight.asl"
+	}
+}
+
+Scope (\_GPE)
+{
+	#include "gpe.asl"
+}

src/mainboard/system76/oryp5/acpi/sleep.asl

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1)
+{
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/oryp5/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: oryp5
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/oryp5/bootblock.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/oryp5/devicetree.cb

@@ -0,0 +1,312 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Disable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 78,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
+	register "SataPortsEnable[2]" = "0"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "1" # HDD (SATA4)
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C/DP
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # WLAN/Bluetooth
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C/DP
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+	# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+	register "PcieClkSrcUsage[8]" = "0x40"
+
+	# PCI Express root port #9 x4, Clock 12 (SSD)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[12]" = "8"
+
+	# PCI Express root port #14 x1, Clock 13 (WLAN)
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	register "PcieClkSrcUsage[13]" = "13"
+
+	# PCI Express root port #15 x1, Clock 14 (GLAN)
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpLtrEnable[14]" = "1"
+	register "PcieClkSrcUsage[14]" = "14"
+
+	# PCI Express root port #16 x1, Clock 15 (Card Reader)
+	register "PcieRpEnable[15]" = "1"
+	register "PcieRpLtrEnable[15]" = "1"
+	register "PcieClkSrcUsage[15]" = "15"
+
+	# PCI Express root port #21 x4, Clock 11 (SSD2)
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpLtrEnable[20]" = "1"
+	register "PcieClkSrcUsage[11]" = "20"
+
+	# Set all clocks sources to the same clock request
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "13"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_B"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x95e6 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # GPU Port
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on      # I2C #0
+			# I2C HID not supported on PNP0f13
+		end
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 off end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on  end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 on  end # PCI Express Port 15
+		device pci 1d.7 on  end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on      # Intel HDA
+			subsystemid 0x1558 0x96e1
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on      # SMBus
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end # tas5825m
+		end
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/oryp5/dsdt.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI 2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/oryp5/gpio.h

@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_C12
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+		PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+		PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1), // NC
+		PAD_CFG_GPI(GPD7, UP_20K, PWROK), // GPD_7
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK
+		PAD_CFG_GPI(GPD9, UP_20K, PWROK), // NC
+		PAD_CFG_NF(GPD10, UP_20K, PWROK, NF1), // NC
+		PAD_CFG_TERM_GPO(GPD11, 1, NONE, DEEP), // LAN_DISABLE#
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
+		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
+		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
+		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
+		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+		PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA#
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
+		PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
+		PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // NC
+		_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT
+		PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_A13, UP_20K, DEEP), // SUSWARN#
+		PAD_CFG_GPI(GPP_A14, UP_20K, DEEP), // NC (test point)
+		PAD_CFG_GPI(GPP_A15, UP_20K, DEEP), // SUS_PWR_ACK#
+		PAD_CFG_GPI(GPP_A16, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_A17, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_A18, UP_20K, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP), // SB_BLON
+		PAD_CFG_GPI(GPP_A20, NONE, DEEP), // PEX_WAKE#
+		PAD_CFG_GPI(GPP_A21, UP_20K, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // WLAN_SSD2_GPIO1
+		PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP), // WLAN_SSD2_GPIO
+		PAD_CFG_GPI(GPP_B0, UP_20K, DEEP), // TPM_PIRQ#
+		PAD_CFG_GPI(GPP_B1, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_RF_KILL_R_N
+		PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // WIFI_RF_KILL_R_N
+		PAD_CFG_GPI(GPP_B5, UP_20K, PLTRST), // NC
+		PAD_CFG_GPI(GPP_B6, UP_20K, PLTRST), // NC
+		PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST), // CR_GPIO_RST#
+		PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST), // CR_GPIO_WAKE#
+		PAD_CFG_GPI(GPP_B9, UP_20K, PLTRST), // NC
+		PAD_CFG_TERM_GPO(GPP_B10, 0, NONE, PLTRST), // NC
+		PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0#
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+		PAD_CFG_GPI(GPP_B15, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_B16, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_B17, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_B18, UP_20K, DEEP), // LPSS_GSPI0_MOSI
+		PAD_CFG_GPI(GPP_B19, UP_20K, DEEP), // NC
+		_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), // SMI#
+		PAD_CFG_GPI(GPP_B21, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI
+		_PAD_CFG_STRUCT(GPP_B23, 0x80880100, 0x3000), // SCI#
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+		PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // GPP_C2_BT_UART_WAKE_N
+		PAD_CFG_GPI(GPP_C3, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_C4, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // M.2_WLAN_WIFI_WAKE_N
+		PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM
+		PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM
+		PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
+		PAD_CFG_GPI(GPP_C9, DN_20K, DEEP), // BOARD_ID1
+		PAD_CFG_GPI(GPP_C10, DN_20K, DEEP), // BOARD_ID2
+		PAD_CFG_GPI(GPP_C11, DN_20K, DEEP), // BOARD_ID3
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+		PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, DEEP), // GPU_EVENT#
+		PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL1#
+		PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, DEEP), // M.2_PLT_RST_CNTRL2#
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // SMD_7411_I2C
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // SMC_7411_I2C
+		PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD ==> NC (test point)
+		PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD ==> NC (test point)
+		PAD_CFG_NF(GPP_C22, UP_20K, DEEP, NF1), // UART2_RTS# (test point), LAN_PLT_RST#
+		PAD_CFG_NF(GPP_C23, UP_20K, DEEP, NF1), // BOARD_ID4
+		PAD_CFG_GPI(GPP_D0, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D1, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D2, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D3, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D4, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUT_CLKREQ0
+		PAD_CFG_GPI(GPP_D7, UP_20K, DEEP), // M.2_BT_PCMIN
+		PAD_CFG_GPI(GPP_D8, UP_20K, DEEP), // M.2_BT_PCMCLK
+		PAD_CFG_GPI(GPP_D9, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D10, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D11, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D12, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), // 10k pull up
+		PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), // 10k pull up
+		PAD_CFG_GPI(GPP_D15, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D16, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), // NC
+		PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), // NC
+		PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), // NC
+		PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), // NC
+		PAD_CFG_GPI(GPP_D21, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D22, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_D23, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_E0, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET
+		PAD_CFG_GPI(GPP_E2, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), // M2_P0_SATA_DEVSLP
+		PAD_CFG_GPI(GPP_E6, UP_20K, DEEP), // NC
+		PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+		PAD_CFG_GPI(GPP_E9, UP_20K, DEEP), // USB_OC0# ==> NC (test point)
+		PAD_CFG_GPI(GPP_E10, UP_20K, DEEP), // USB_OC1# ==> NC (test point)
+		PAD_CFG_GPI(GPP_E11, UP_20K, DEEP), // USB_OC2# ==> NC (test point)
+		PAD_CFG_GPI(GPP_E12, UP_20K, DEEP), // USB_OC3# ==> NC (test point)
+		PAD_CFG_GPI(GPP_F0, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_PEDET
+		PAD_CFG_GPI(GPP_F2, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F3, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F4, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F5, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP
+		PAD_CFG_GPI(GPP_F7, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F8, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F9, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC
+		PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // GPP_F11
+		PAD_CFG_GPI(GPP_F12, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT
+		PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // 10k pull up to H_SKTOCC_N
+		PAD_CFG_GPI(GPP_F15, UP_20K, DEEP), // USB_OC4# ==> NC (test point)
+		PAD_CFG_GPI(GPP_F16, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F17, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_F18, UP_20K, DEEP), // USB_OC7# ==> NC (test point)
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+		PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
+		PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // NC
+		PAD_NC(GPP_G1, NONE), // CNVI_WIGIG_DET#
+		PAD_CFG_GPI(GPP_G2, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_G4, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_G5, UP_20K, DEEP), // NC
+		_PAD_CFG_STRUCT(GPP_G6, 0x40880100, 0x0000), // SWI#
+		PAD_CFG_GPI(GPP_G7, UP_20K, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_H0, 0, NONE, PLTRST), // NC
+		PAD_CFG_TERM_GPO(GPP_H1, 0, NONE, PLTRST), // NC
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ9_PEG#
+		PAD_CFG_TERM_GPO(GPP_H3, 0, NONE, PLTRST), // NC
+		PAD_CFG_TERM_GPO(GPP_H4, 0, NONE, PLTRST), // NC
+		PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ12_SSD2#
+		PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ13_SSD1#
+		PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // GPP_H_0_SRCCLKREQB_14
+		PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CLK_REQ15_LAN#
+		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CLK_REQ16_CARD#
+		PAD_CFG_GPI(GPP_H10, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H11, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H12, UP_20K, DEEP), // GPP_H_12 (test point)
+		PAD_CFG_GPI(GPP_H13, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H14, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H15, UP_20K, DEEP), // GPP_H15
+		PAD_CFG_GPI(GPP_H16, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H17, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H18, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H19, UP_20K, DEEP), // GPIO_CARD1
+		PAD_CFG_GPI(GPP_H20, UP_20K, DEEP), // GPIO_CARD
+		PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), // 4.7k pull up, 20k pull down
+		PAD_CFG_GPI(GPP_H22, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_H23, UP_20K, DEEP), // NC
+		_PAD_CFG_STRUCT(GPP_I0, 0x46880100, 0x0000), // G_DP_DHPD_A
+		_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // HDMI_HPD
+		_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // G_DP_DHPD_E
+		PAD_CFG_GPI(GPP_I3, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HDP
+		PAD_CFG_GPI(GPP_I5, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_I6, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_I7, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_I8, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_I9, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_I10, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // H_SKTOCC_N
+		PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
+		PAD_CFG_GPI(GPP_I13, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_I14, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
+		PAD_CFG_GPI(GPP_J2, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_J3, UP_20K, DEEP), // NC
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_VRI_DT_BT_UART0_RTS
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP
+		PAD_CFG_GPI(GPP_J8, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // CNVI_MFUART2_TXD
+		PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // NC
+		PAD_NC(GPP_K0, NONE), // NC
+		PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K3, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K5, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K6, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // SATA_M2_PWR_EN1
+		PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), // SATA_M2_PWR_EN2
+		PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K12, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K13, UP_20K, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_K14, 0, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point), 7411_TEST_R
+		PAD_CFG_GPI(GPP_K15, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K16, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K17, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K18, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K19, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K20, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K21, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K22, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_K23, UP_20K, DEEP), // NC
+};
+
+#endif
+
+#endif

src/mainboard/system76/oryp5/hda_verb.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155896e1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155896e1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11050),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451130),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/oryp5/ramstage.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/oryp5/romstage.c

@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {.read_type = NOT_EXISTING},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {.read_type = NOT_EXISTING},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 75, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+	.rcomp_targets = { 50, 25, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}