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drivers/intel/fsp2_0: load and relocate FSPS in cbmem

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The FSPS component loading was just loading to any memory address
listed in the header. That could be anywhere in the address space
including ramstage itself -- let alone corrupting the OS memory on
S3 resume. Remedy this by loading and relocating FSPS into cbmem.
The UEFI 2.4 header files include path are selected to provide the
types necessary for FSP relocation.

BUG=chrome-os-partner:52679

Change-Id: Iaba103190731fc229566a3b0231cf967522040db
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15742
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
This commit is contained in:
Aaron Durbin
2016-07-18 00:35:42 -05:00
parent d04639b3d6
commit 32ac01823b
5 changed files with 47 additions and 13 deletions
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7
src/soc/intel/apollolake/chip.c
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@ -25,7 +25,6 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <memrange.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
@ -192,7 +191,6 @@ static void pcie_override_devicetree_after_silicon_init(void)
static void soc_init(void *data)
{
struct range_entry range;
struct global_nvs_t *gnvs;
/* Save VBT info and mapping */
@ -203,10 +201,7 @@ static void soc_init(void *data)
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* TODO: tigten this resource range */
/* TODO: fix for S3 resume, as this would corrupt OS memory */
range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
fsp_silicon_init(&range);
fsp_silicon_init();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);