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intel/fsp: Update cannonlake fsp header

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Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17
Offset 15h Speed report incorrectly issue.

BUG=None
TEST=Boot up with meowth platform and run dmidecode to see two dimm
entries under Type 17.

Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25378
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao
2018-03-26 18:37:16 -07:00
committed by Martin Roth
parent 2a50a1f534
commit 32c3069fd7
1 changed files with 1 additions and 0 deletions
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src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h
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@@ -202,6 +202,7 @@ typedef struct {
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
} DIMM_INFO;
typedef struct {