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Rangeley: Fix incorrect BCLK

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Not all Rangeley SKUs have a fixed 100MHz BCLK.

As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0].
Using fixed BCLK was causing wrong values of core frequencies in _PSS table
for SKUs that do not have BCLK=100MHz.

Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f
Signed-off-by: Hannah Williams <hannah.williams@dell.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-11-02 09:39:36 +02:00
committed by Patrick Georgi
parent 3042af6256
commit 32c8de10b0
3 changed files with 23 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/intel/common/fsb.c
View File

@@ -32,6 +32,7 @@ static int get_fsb_tsc(int *fsb, int *ratio)
static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
static const short rangeley_fsb[4] = { 83, 100, 133, 116 };
msr_t msr;
get_fms(&c, cpuid_eax(1));
@@ -56,10 +57,13 @@ static int get_fsb_tsc(int *fsb, int *ratio)
case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
case 0x3c: /* Haswell BCLK fixed at 100MHz */
case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
case 0x4d: /* Rangeley BCLK fixed at 100MHz */
*fsb = 100;
*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
break;
case 0x4d: /* Rangeley */
*fsb = rangeley_fsb[rdmsr(MSR_FSB_FREQ).lo & 3];
*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
break;
default:
return -2;
}