From 32f3311f3e4b891fea3aad5dac8cff53c2a26db7 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Tue, 14 Sep 2021 10:36:50 -0600
Subject: [PATCH] Add oryp8

Change-Id: I28611cf59c9509726af250411a867a1898ec7ace
---
 src/mainboard/system76/oryp8/Kconfig          |   83 ++
 src/mainboard/system76/oryp8/Kconfig.name     |    2 +
 src/mainboard/system76/oryp8/Makefile.inc     |    5 +
 .../system76/oryp8/acpi/backlight.asl         |   30 +
 src/mainboard/system76/oryp8/acpi/dgpu.asl    |   32 +
 .../system76/oryp8/acpi/mainboard.asl         |   14 +
 src/mainboard/system76/oryp8/acpi/sleep.asl   |   46 +
 src/mainboard/system76/oryp8/board_info.txt   |    8 +
 src/mainboard/system76/oryp8/bootblock.c      |   11 +
 src/mainboard/system76/oryp8/cmos.default     |    3 +
 src/mainboard/system76/oryp8/cmos.layout      |   43 +
 src/mainboard/system76/oryp8/data.vbt         |  Bin 0 -> 8704 bytes
 src/mainboard/system76/oryp8/devicetree.cb    |  252 ++++
 src/mainboard/system76/oryp8/dsdt.asl         |   32 +
 src/mainboard/system76/oryp8/gpio.h           |  297 +++++
 src/mainboard/system76/oryp8/hda_verb.c       |   30 +
 src/mainboard/system76/oryp8/ramstage.c       |   27 +
 src/mainboard/system76/oryp8/romstage.c       |   34 +
 src/mainboard/system76/oryp8/tas5825m.c       | 1080 +++++++++++++++++
 19 files changed, 2029 insertions(+)
 create mode 100644 src/mainboard/system76/oryp8/Kconfig
 create mode 100644 src/mainboard/system76/oryp8/Kconfig.name
 create mode 100644 src/mainboard/system76/oryp8/Makefile.inc
 create mode 100644 src/mainboard/system76/oryp8/acpi/backlight.asl
 create mode 100644 src/mainboard/system76/oryp8/acpi/dgpu.asl
 create mode 100644 src/mainboard/system76/oryp8/acpi/mainboard.asl
 create mode 100644 src/mainboard/system76/oryp8/acpi/sleep.asl
 create mode 100644 src/mainboard/system76/oryp8/board_info.txt
 create mode 100644 src/mainboard/system76/oryp8/bootblock.c
 create mode 100644 src/mainboard/system76/oryp8/cmos.default
 create mode 100644 src/mainboard/system76/oryp8/cmos.layout
 create mode 100644 src/mainboard/system76/oryp8/data.vbt
 create mode 100644 src/mainboard/system76/oryp8/devicetree.cb
 create mode 100644 src/mainboard/system76/oryp8/dsdt.asl
 create mode 100644 src/mainboard/system76/oryp8/gpio.h
 create mode 100644 src/mainboard/system76/oryp8/hda_verb.c
 create mode 100644 src/mainboard/system76/oryp8/ramstage.c
 create mode 100644 src/mainboard/system76/oryp8/romstage.c
 create mode 100644 src/mainboard/system76/oryp8/tas5825m.c

diff --git a/src/mainboard/system76/oryp8/Kconfig b/src/mainboard/system76/oryp8/Kconfig
new file mode 100644
index 0000000000..65fa556a23
--- /dev/null
+++ b/src/mainboard/system76/oryp8/Kconfig
@@ -0,0 +1,83 @@
+if BOARD_SYSTEM76_ORYP8
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_TIGERLAKE
+	select SOC_INTEL_TIGERLAKE_PCH_H
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_OPTION_TABLE
+
+config MAINBOARD_DIR
+	string
+	default "system76/oryp8"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "oryp8"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Oryx Pro"
+
+config MAINBOARD_VERSION
+	string
+	default "oryp8"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config DIMM_MAX
+	int
+	default 4 # Hack to make soc code work
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config DRIVERS_SYSTEM76_DGPU_DEVICE
+	hex
+	default 0x01
+
+config MAX_CPUS
+	int
+	default 16
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config POST_DEVICE
+	bool
+	default n
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+endif
diff --git a/src/mainboard/system76/oryp8/Kconfig.name b/src/mainboard/system76/oryp8/Kconfig.name
new file mode 100644
index 0000000000..236b8c87cc
--- /dev/null
+++ b/src/mainboard/system76/oryp8/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ORYP8
+	bool "oryp8"
diff --git a/src/mainboard/system76/oryp8/Makefile.inc b/src/mainboard/system76/oryp8/Makefile.inc
new file mode 100644
index 0000000000..649edffda6
--- /dev/null
+++ b/src/mainboard/system76/oryp8/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c
diff --git a/src/mainboard/system76/oryp8/acpi/backlight.asl b/src/mainboard/system76/oryp8/acpi/backlight.asl
new file mode 100644
index 0000000000..12aaab6e4f
--- /dev/null
+++ b/src/mainboard/system76/oryp8/acpi/backlight.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0) {
+       Name (BRIG, Package (22) {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}
diff --git a/src/mainboard/system76/oryp8/acpi/dgpu.asl b/src/mainboard/system76/oryp8/acpi/dgpu.asl
new file mode 100644
index 0000000000..ba1e2d7d0f
--- /dev/null
+++ b/src/mainboard/system76/oryp8/acpi/dgpu.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.PEG1) {
+	Device (DEV0) {
+		Name(_ADR, 0x00000000)
+		Name(SSID, 0x00000000)
+
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
+		Field (PCIC, DwordAcc, NoLock, Preserve) {
+			Offset (0x40),
+			NVID, 32
+		}
+
+		Name (_PR0, Package () { PWRR })
+		Name (_PR3, Package () { PWRR })
+		PowerResource (PWRR, 0, 0) {
+			Name (_STA, 1)
+
+			Method (_ON) {
+				^^NVID = ^^SSID
+				Printf("GPU _ON %o", ToHexString(^^SSID))
+				_STA = 1
+			}
+
+			Method (_OFF) {
+				^^SSID = ^^NVID
+				Printf("GPU _OFF %o", ToHexString(^^SSID))
+				_STA = 0
+			}
+		}
+	}
+}
diff --git a/src/mainboard/system76/oryp8/acpi/mainboard.asl b/src/mainboard/system76/oryp8/acpi/mainboard.asl
new file mode 100644
index 0000000000..aff8765c6e
--- /dev/null
+++ b/src/mainboard/system76/oryp8/acpi/mainboard.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "dgpu.asl"
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
diff --git a/src/mainboard/system76/oryp8/acpi/sleep.asl b/src/mainboard/system76/oryp8/acpi/sleep.asl
new file mode 100644
index 0000000000..ceb8bacb12
--- /dev/null
+++ b/src/mainboard/system76/oryp8/acpi/sleep.asl
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+	PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+	}
+}
diff --git a/src/mainboard/system76/oryp8/board_info.txt b/src/mainboard/system76/oryp8/board_info.txt
new file mode 100644
index 0000000000..544c341cf5
--- /dev/null
+++ b/src/mainboard/system76/oryp8/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: oryp8
+Category: laptop
+Release year: 2021
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/oryp8/bootblock.c b/src/mainboard/system76/oryp8/bootblock.c
new file mode 100644
index 0000000000..44489dfa6d
--- /dev/null
+++ b/src/mainboard/system76/oryp8/bootblock.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}
diff --git a/src/mainboard/system76/oryp8/cmos.default b/src/mainboard/system76/oryp8/cmos.default
new file mode 100644
index 0000000000..c2fded82a3
--- /dev/null
+++ b/src/mainboard/system76/oryp8/cmos.default
@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+preserve_smmstore=0
diff --git a/src/mainboard/system76/oryp8/cmos.layout b/src/mainboard/system76/oryp8/cmos.layout
new file mode 100644
index 0000000000..bf6e103a3a
--- /dev/null
+++ b/src/mainboard/system76/oryp8/cmos.layout
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+408	1	h	1	preserve_smmstore
+#409	2	e	7	power_on_after_fail
+412	4	e	6	debug_level
+984	16	h	0	check_sum
+
+enumerations
+
+1	0	Disable
+1	1	Enable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+7	0	Disable
+7	1	Enable
+7	2	Keep
+
+checksums
+
+checksum 408 983 984
diff --git a/src/mainboard/system76/oryp8/data.vbt b/src/mainboard/system76/oryp8/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..5641c17f76d843dfaf63eff3e2bd7105abb2a8bd
GIT binary patch
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diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb
new file mode 100644
index 0000000000..3cd49a6b63
--- /dev/null
+++ b/src/mainboard/system76/oryp8/devicetree.cb
@@ -0,0 +1,252 @@
+chip soc/intel/tigerlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# ACPI (soc/intel/tigerlake/acpi.c)
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# CPU (soc/intel/tigerlake/cpu.c)
+	# Power limits
+	register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 90,
+	}"
+	register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 90,
+	}"
+
+# Finalize (soc/intel/tigerlake/finalize.c)
+	# PM Timer Disabled, saves power
+	register "PmTimerDisabled" = "1"
+
+# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
+	# Enable C6 DRAM
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
+	# Acoustic settings
+	register "AcousticNoiseMitigation" = "1"
+	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
+	register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
+	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
+	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
+	register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
+
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Read LPM_EN, make sure to invert the bits
+	# sudo devmem2 0xfe001c78
+	# 0x9
+	register "LpmStateDisableMask" = "
+		LPM_S0i2_1 |
+		LPM_S0i2_2 |
+		LPM_S0i3_1 |
+		LPM_S0i3_2 |
+		LPM_S0i3_3 |
+		LPM_S0i3_4
+	"
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "10"
+
+# PM Util (soc/intel/tigerlake/pmutil.c)
+	# GPE configuration
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	# 0x432
+	register "pmc_gpe0_dw0" = "PMC_GPP_R"
+	register "pmc_gpe0_dw1" = "PMC_GPP_B"
+	register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x65f1 inherit
+
+		#From CPU EDS(575683)
+		device ref system_agent on end
+		device ref peg1 on
+			# PCIe PEG1 x16, Clock 9 (DGPU)
+			register "PcieClkSrcUsage[9]" = "0x41"
+			register "PcieClkSrcClkReq[9]" = "9"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				register "enable_delay_ms" = "16"
+				register "enable_off_delay_ms" = "4"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "4"
+				#TODO: Support disable/enable CPU RP clock
+				register "srcclk_pin" = "-1" # PEG_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref igpu on
+			# DDIA is eDP
+			register "DdiPortAConfig" = "1"
+			register "DdiPortAHpd" = "1"
+			register "DdiPortADdc" = "0"
+
+			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+		end
+		device ref dptf on
+			register "Device4Enable" = "1"
+		end
+		device ref peg0 on
+			# PCIe PEG0 x4, Clock 7 (SSD1)
+			register "PcieClkSrcUsage[7]" = "0x40"
+			register "PcieClkSrcClkReq[7]" = "7"
+
+			#TODO: Hybrid storage mode?
+			register "HybridStorageMode" = "0"
+		end
+		device ref tbt_pcie_rp0 on end # TYPEC1
+		device ref gna on end
+		device ref north_xhci on # TYPEC1
+			register "TcssXhciEn" = "1"
+		end
+		device ref tbt_dma0 on end # TYPEC1
+
+		# From PCH EDS(615985)
+		device ref cnvi_bt on end
+		device ref south_xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
+		end
+		device ref shared_ram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""SYNA1202""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+		device ref heci1 on
+			#TODO Disable ME and HECI
+			register "HeciEnabled" = "1"
+		end
+		device ref uart2 on
+			# Debug console
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
+		end
+		device ref sata on
+			register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
+		end
+		device ref pcie_rp5 on
+			# PCIe root port #5 x1, Clock 8 (GLAN)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieClkSrcUsage[8]" = "4"
+			register "PcieClkSrcClkReq[8]" = "8"
+		end
+		device ref pcie_rp6 on
+			# PCIe root port #6 x1, Clock 10 (CARD)
+			register "PcieRpEnable[5]" = "1"
+			register "PcieRpLtrEnable[5]" = "1"
+			register "PcieClkSrcUsage[10]" = "5"
+			register "PcieClkSrcClkReq[10]" = "10"
+		end
+		device ref pcie_rp8 on
+			# PCIe root port #8 x1, Clock 2 (WLAN)
+			register "PcieRpEnable[7]" = "1"
+			register "PcieRpLtrEnable[7]" = "1"
+			register "PcieClkSrcUsage[2]" = "7"
+			register "PcieClkSrcClkReq[2]" = "2"
+		end
+		device ref pcie_rp9 on
+			# PCIe root port #9 x4, Clock 6 (SSD2)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[6]" = "8"
+			register "PcieClkSrcClkReq[6]" = "6"
+		end
+		device ref pch_espi on
+			# LPC configuration from lspci -s 1f.0 -xxx
+			# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+			register "gen1_dec" = "0x000c0081"
+			# Address 0x88: Decode 0x68 - 0x6F (PMC)
+			register "gen2_dec" = "0x00040069"
+			# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+			register "gen3_dec" = "0x00fc0E01"
+			# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+			register "gen4_dec" = "0x00fc0F01"
+			# LPC TPM
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref pmc hidden end
+		device ref hda on
+			register "PchHdaAudioLinkHdaEnable" = "1"
+		end
+		device ref smbus on
+			register "SmbusEnable" = "1"
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+		end
+		device ref fast_spi on end
+	end
+end
diff --git a/src/mainboard/system76/oryp8/dsdt.asl b/src/mainboard/system76/oryp8/dsdt.asl
new file mode 100644
index 0000000000..09b20de5df
--- /dev/null
+++ b/src/mainboard/system76/oryp8/dsdt.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/tigerlake/acpi/southbridge.asl>
+		#include <soc/intel/tigerlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/oryp8/gpio.h b/src/mainboard/system76/oryp8/gpio.h
new file mode 100644
index 0000000000..6a821459f9
--- /dev/null
+++ b/src/mainboard/system76/oryp8/gpio.h
@@ -0,0 +1,297 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F8
+#define DGPU_PWR_EN GPP_F9
+#define DGPU_GC6 GPP_K11
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_GPO(DGPU_RST_N, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(DGPU_PWR_EN, 0, DEEP), // DGPU_PWR_EN
+};
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_CFG_GPI(GPD11, NONE, PWROK),
+	_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS#_EC
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_A10, UP_20K, DEEP), // SERIRQ_ESPI_ALERT0
+	PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
+	PAD_CFG_GPI(GPP_A14, NONE, DEEP),
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_B1, NONE, DEEP), // VRALERT#_PD
+	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B5, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ2#
+	PAD_CFG_GPI(GPP_B8, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B10, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_CFG_GPO(GPP_B15, 1, DEEP), // SATA_M2_PWR_EN1
+	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
+	PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B20, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT strap
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // CPUNSSC clock
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT
+	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE#
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // PCH_I2C_SCL
+	PAD_CFG_GPI(GPP_C5, NONE, DEEP), // eSPI/LPC select strap
+	PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SWI#
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_GPI(GPP_C12, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+	PAD_CFG_GPI(GPP_C14, NONE, DEEP), // GPP_C14_RTD3
+	PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // I2C_SDA_Pantone
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // I2C_SCL_Pantone
+	//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_GPO(GPP_C22, 0, DEEP), // ROM_I2C_EN
+	PAD_CFG_GPI(GPP_C23, NONE, DEEP), // SMI#
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), // SML1CLK
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNVI_RF_RST#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
+	PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
+	PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+	PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), // SML1_DATA
+	PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D18, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D19, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D20, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+	PAD_CFG_GPO(GPP_D23, 1, DEEP), // GPU_EVENT#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // M.2_SSD1_PEDET
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), // M2_P1_SATA_DEVSLP
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
+	PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
+	PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3#
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+	PAD_CFG_GPO(GPP_F1, 1, DEEP), // LAN_PLT_RST#
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST), // GPIO_LANRTD3
+	PAD_CFG_GPO(GPP_F3, 0, PLTRST), // GPP_F3_TBT_FORCE_PWR
+	PAD_CFG_GPO(GPP_F4, 1, DEEP), // SATA_PWR_EN
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F6, 1, DEEP), // GPIO_LAN_EN
+	PAD_CFG_GPO(GPP_F7, 0, DEEP), // PCH_GPIO_PK_MUTE
+	//PAD_CFG_GPO(GPP_F8, 1, DEEP), // DGPU_RST#_PCH
+	//PAD_CFG_GPO(GPP_F9, 1, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC
+	PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
+	PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F17, 1, DEEP), // SB_BLON
+	PAD_CFG_GPO(GPP_F18, 1, DEEP), // EAPD_MODE
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+	PAD_NC(GPP_F22, NONE), // PCH_VNN_CTRL
+	PAD_CFG_GPO(GPP_F23, 1, PLTRST), // CARD_RTD3_RST#
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+	PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+	PAD_CFG_GPO(GPP_G6, 1, DEEP), // GPIO_CARD_AUX
+	PAD_CFG_GPO(GPP_G7, 1, DEEP), // GPIO_CARD
+	PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
+	PAD_CFG_GPI(GPP_G9, NONE, DEEP), // GPP_G9
+	PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
+	PAD_CFG_GPI(GPP_G11, NONE, DEEP), // GPP_G11
+	PAD_NC(GPP_G12, NATIVE), // GPP_G12_TBT_LSX_TXD
+	PAD_NC(GPP_G13, NATIVE), // GPP_G13_TBT_LSX0_RXD
+	PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
+	PAD_CFG_GPI(GPP_G15, NONE, DEEP), // GPP_G15
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // SSD_CLKREQ6#
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SDD_PEX4_CLKREQ7#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // LAN_CLKREQ8#
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // PEG_CLKREQ9#
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // CARD_CLKREQ10#
+	PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H6, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPI(GPP_H7, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H9, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H10, NONE, DEEP), // SML2CLK
+	PAD_CFG_GPI(GPP_H11, NONE, DEEP), // SML2DATA
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H12
+	PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK
+	PAD_CFG_GPI(GPP_H14, NONE, DEEP), // SML3DATA
+	PAD_CFG_GPI(GPP_H15, NONE, PLTRST), // SML3ALERT#
+	PAD_CFG_GPI(GPP_H16, NONE, DEEP), // SML4CLK
+	PAD_CFG_GPO(GPP_H17, 1, DEEP), // SATA_M2_PWR_EN2
+	PAD_CFG_GPI(GPP_H18, NONE, DEEP), // GPP_H18
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H20, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H23, 1, DEEP), // GPP_H23_SDD1_RST#
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
+	_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // G_DP_DHPD_E
+	_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // HDMI_HPD
+	_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // CPU_DPIP0_HPD
+	PAD_CFG_GPI(GPP_I4, NONE, DEEP),
+	PAD_CFG_GPI(GPP_I5, NONE, DEEP),
+	PAD_CFG_GPI(GPP_I6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+	PAD_CFG_GPI(GPP_I8, NONE, DEEP),
+	PAD_CFG_GPO(GPP_I9, 1, DEEP), // GGPP_I9_SDD2_RST#
+	PAD_CFG_GPI(GPP_I10, DN_20K, DEEP),
+	PAD_CFG_GPI(GPP_I11, NONE, PLTRST), // USB_OC4#
+	PAD_CFG_GPI(GPP_I12, NONE, PLTRST), // USB_OC5#
+	PAD_CFG_GPI(GPP_I13, NONE, PLTRST), // USB_OC6#
+	PAD_CFG_GPI(GPP_I14, NONE, PLTRST), // USB_OC7#
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // GPP_J1
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_CFG_GPI(GPP_J8, NONE, PLTRST), // GPIO4_NVDD_EN
+	PAD_CFG_GPI(GPP_J9, NONE, DEEP),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_GPO(GPP_K0, 0, DEEP), // OVRM
+	PAD_CFG_GPI(GPP_K1, NONE, DEEP),
+	PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R
+	PAD_CFG_GPI(GPP_K3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_K4, NONE, DEEP),
+	PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+	PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1), // SB_IEDP_HPD
+	PAD_CFG_GPI(GPP_K7, NONE, DEEP),
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+	PAD_CFG_GPI(GPP_K11, NONE, PLTRST), // GC6_FB_EN_PCH
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_R6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_R7, NONE, DEEP),
+	PAD_CFG_GPI(GPP_R8, NONE, DEEP), // CHIP_ID1
+	PAD_CFG_GPI(GPP_R9, NONE, DEEP), // GSYNC_DET
+	PAD_CFG_GPI(GPP_R10, NONE, DEEP), // DDS_DET
+	PAD_CFG_GPI(GPP_R11, NONE, DEEP), // CHIP_ID0
+	PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_GPI(GPP_R13, NONE, DEEP),
+	PAD_CFG_GPI(GPP_R14, NONE, DEEP),
+	PAD_CFG_GPI(GPP_R15, NONE, DEEP),
+	PAD_CFG_GPI(GPP_R16, NONE, DEEP), // BL_PWM_EN_EC
+	PAD_CFG_GPI(GPP_R17, NONE, DEEP), // PLVDD_RST_EC
+	PAD_CFG_GPI(GPP_R18, NONE, DEEP), // MUX_CTRL_BIOS
+	PAD_CFG_GPI(GPP_R19, NONE, DEEP), // PS8461_SW
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_CFG_GPI(GPP_S0, NONE, DEEP),
+	PAD_CFG_GPI(GPP_S1, NONE, DEEP),
+	PAD_CFG_GPI(GPP_S2, NONE, DEEP),
+	PAD_CFG_GPI(GPP_S3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_S4, NONE, DEEP),
+	PAD_CFG_GPI(GPP_S5, NONE, DEEP),
+	PAD_CFG_GPI(GPP_S6, NONE, DEEP), // DMIC_CLK0
+	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DATA0
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/system76/oryp8/hda_verb.c b/src/mainboard/system76/oryp8/hda_verb.c
new file mode 100644
index 0000000000..b068a400a4
--- /dev/null
+++ b/src/mainboard/system76/oryp8/hda_verb.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865f1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865f1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/oryp8/ramstage.c b/src/mainboard/system76/oryp8/ramstage.c
new file mode 100644
index 0000000000..e50a7ca55e
--- /dev/null
+++ b/src/mainboard/system76/oryp8/ramstage.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// PEG0 Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// PEG1 Config
+	params->CpuPcieRpAdvancedErrorReporting[1] = 0;
+	params->CpuPcieRpLtrEnable[1] = 1;
+	params->CpuPcieRpPtmEnabled[1] = 0;
+
+	// IOM config
+	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[8] = 1; // TYPEC1
+	params->UsbTcPortEn = 1;
+
+	// Low latency legacy I/O
+	params->PchLegacyIoLowLatency = 1;
+
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/oryp8/romstage.c b/src/mainboard/system76/oryp8/romstage.c
new file mode 100644
index 0000000000..bf9bcf6971
--- /dev/null
+++ b/src/mainboard/system76/oryp8/romstage.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/util.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_ddr4_cfg board_cfg = {
+	// dq_map unused on DDR4
+	// dqs_map unused on DDR4
+
+	.dq_pins_interleaved = 1,
+	.ect = 0,
+};
+
+static const struct spd_info spd = {
+	.topology = SODIMM,
+	.smbus_info[0] = {
+		.addr_dimm0 = 0x50,
+	},
+	.smbus_info[1] = {
+		.addr_dimm0 = 0x52,
+	},
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd) {
+	// Enable M.2 PCIE 4.0 and PEG1
+	mupd->FspmConfig.CpuPcieRpEnableMask = 0b11;
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	const bool half_populated = false;
+	meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated);
+}
diff --git a/src/mainboard/system76/oryp8/tas5825m.c b/src/mainboard/system76/oryp8/tas5825m.c
new file mode 100644
index 0000000000..5c433227b2
--- /dev/null
+++ b/src/mainboard/system76/oryp8/tas5825m.c
@@ -0,0 +1,1080 @@
+#include <delay.h>
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+#define R(F) { \
+	res = F; \
+	if (res < 0) return res; \
+}
+
+#define amp_write_at(A, V) R(tas5825m_write_at(dev, A, V))
+
+#define amp_write_block_at(A, ...) { \
+	const uint8_t _values[] = __VA_ARGS__; \
+	R(tas5825m_write_block_at(dev, A, _values, ARRAY_SIZE(_values))); \
+}
+
+#define amp_set_page(P) R(tas5825m_set_page(dev, P))
+
+#define amp_set_book(B) R(tas5825m_set_book(dev, B))
+
+int tas5825m_setup(struct device * dev, int id) {
+	int res = 0;
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x60, 0x00);
+		amp_write_at(0x63, 0x03);
+		amp_write_at(0x64, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x02);
+		amp_write_at(0x01, 0x11);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x46, 0x11);
+	}
+
+	{
+		amp_set_page(0x00);
+
+		amp_write_at(0x02, 0x00);
+		amp_write_at(0x53, 0x00);
+		amp_write_at(0x54, 0x00);
+		amp_write_at(0x29, 0x7C);
+		amp_write_at(0x03, 0x02);
+	}
+
+	mdelay(5);
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	{
+		amp_set_page(0x00);
+
+		amp_write_at(0x29, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x12);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x48, 0x0C);
+	}
+
+	amp_set_book(0x64);
+
+	{
+		amp_set_page(0x01);
+
+		amp_write_block_at(0x08, {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00
+		});
+
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC
+		});
+
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x65, {
+			0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00,
+			0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84,
+			0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02,
+			0x60, 0x00, 0x01
+		});
+	}
+
+	{
+		amp_set_page(0x02);
+
+		amp_write_block_at(0x08, {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04
+		});
+
+		amp_write_block_at(0x27, {
+			0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31,
+			0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31,
+			0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80,
+			0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D
+		});
+
+		amp_write_block_at(0x46, {
+			0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F,
+			0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68,
+			0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B,
+			0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84
+		});
+
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E,
+			0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0,
+			0x1C, 0x11, 0xAB
+		});
+	}
+
+	{
+		amp_set_page(0x03);
+
+		amp_write_block_at(0x08, {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10
+		});
+
+		amp_write_block_at(0x27, {
+			0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26,
+			0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40,
+			0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11,
+			0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C
+		});
+
+		amp_write_block_at(0x46, {
+			0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F,
+			0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27,
+			0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82,
+			0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2
+		});
+
+		amp_write_block_at(0x65, {
+			0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0,
+			0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0,
+			0x1C, 0x51, 0xBB
+		});
+	}
+
+	{
+		amp_set_page(0x04);
+
+		amp_write_block_at(0x08, {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11
+		});
+
+		amp_write_block_at(0x27, {
+			0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98,
+			0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30,
+			0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26,
+			0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10
+		});
+
+		amp_write_block_at(0x46, {
+			0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2,
+			0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00,
+			0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2,
+			0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84
+		});
+
+		amp_write_block_at(0x65, {
+			0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0,
+			0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0,
+			0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80,
+			0x27, 0x80, 0xEA
+		});
+	}
+
+	{
+		amp_set_page(0x05);
+
+		amp_write_block_at(0x08, {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60
+		});
+
+		amp_write_block_at(0x27, {
+			0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00,
+			0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06,
+			0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51,
+			0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3
+		});
+
+		amp_write_block_at(0x46, {
+			0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0,
+			0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2,
+			0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00,
+			0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88
+		});
+
+		amp_write_block_at(0x65, {
+			0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE,
+			0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88,
+			0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86,
+			0xC1, 0x01, 0x9D
+		});
+	}
+
+	{
+		amp_set_page(0x06);
+
+		amp_write_block_at(0x08, {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00
+		});
+
+		amp_write_block_at(0x27, {
+			0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03,
+			0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04,
+			0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26,
+			0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68
+		});
+
+		amp_write_block_at(0x46, {
+			0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60,
+			0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80,
+			0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82,
+			0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0
+		});
+
+		amp_write_block_at(0x65, {
+			0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0,
+			0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86,
+			0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84,
+			0x82, 0x04, 0x07
+		});
+	}
+
+	{
+		amp_set_page(0x07);
+
+		amp_write_block_at(0x08, {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00
+		});
+
+		amp_write_block_at(0x27, {
+			0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04,
+			0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03,
+			0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00,
+			0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07
+		});
+
+		amp_write_block_at(0x46, {
+			0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57,
+			0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82,
+			0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C,
+			0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0
+		});
+
+		amp_write_block_at(0x65, {
+			0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80,
+			0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4,
+			0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4,
+			0x1F, 0x31, 0xA8
+		});
+	}
+
+	{
+		amp_set_page(0x08);
+
+		amp_write_block_at(0x08, {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11
+		});
+
+		amp_write_block_at(0x27, {
+			0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04,
+			0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71,
+			0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71,
+			0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27
+		});
+
+		amp_write_block_at(0x46, {
+			0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B,
+			0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00,
+			0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44,
+			0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84
+		});
+
+		amp_write_block_at(0x65, {
+			0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0,
+			0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0,
+			0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86,
+			0xA1, 0x01, 0xC6
+		});
+	}
+
+	{
+		amp_set_page(0x09);
+
+		amp_write_block_at(0x08, {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00
+		});
+
+		amp_write_block_at(0x27, {
+			0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11,
+			0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11,
+			0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80,
+			0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00
+		});
+
+		amp_write_block_at(0x46, {
+			0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81,
+			0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44,
+			0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43,
+			0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02
+		});
+
+		amp_write_block_at(0x65, {
+			0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84,
+			0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80,
+			0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84,
+			0xC3, 0x03, 0x5F
+		});
+	}
+
+	{
+		amp_set_page(0x0A);
+
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11
+		});
+
+		amp_write_block_at(0x27, {
+			0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03,
+			0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00,
+			0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98,
+			0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43
+		});
+
+		amp_write_block_at(0x46, {
+			0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51,
+			0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40,
+			0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00,
+			0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C
+		});
+
+		amp_write_block_at(0x65, {
+			0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0,
+			0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02,
+			0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84,
+			0xD0, 0x04, 0x09
+		});
+	}
+
+	{
+		amp_set_page(0x0B);
+
+		amp_write_block_at(0x08, {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80
+		});
+
+		amp_write_block_at(0x27, {
+			0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00,
+			0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01,
+			0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01,
+			0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50
+		});
+
+		amp_write_block_at(0x46, {
+			0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC,
+			0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68,
+			0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78,
+			0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84
+		});
+
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84,
+			0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08,
+			0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08,
+			0x60, 0x06, 0x12
+		});
+	}
+
+	{
+		amp_set_page(0x0C);
+
+		amp_write_block_at(0x08, {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01
+		});
+
+		amp_write_block_at(0x27, {
+			0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04,
+			0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00,
+			0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11,
+			0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D
+		});
+
+		amp_write_block_at(0x46, {
+			0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3,
+			0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82,
+			0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81,
+			0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80
+		});
+
+		amp_write_block_at(0x65, {
+			0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00,
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F,
+			0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84,
+			0xC2, 0x04, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x0D);
+
+		amp_write_block_at(0x08, {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18
+		});
+
+		amp_write_block_at(0x27, {
+			0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00,
+			0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20,
+			0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D,
+			0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44
+		});
+
+		amp_write_block_at(0x46, {
+			0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10,
+			0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA,
+			0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0,
+			0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x65, {
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x18);
+
+		amp_write_block_at(0x30, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1B);
+
+		amp_write_block_at(0x6C, {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x1C);
+
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1C);
+
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1C);
+
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1C);
+
+		amp_write_block_at(0x54, {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1C);
+		amp_write_block_at(0x74, {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x1D);
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1D);
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1D);
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x5B, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x7A, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x1E);
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1E);
+
+		amp_write_block_at(0x0C, {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1E);
+
+		amp_write_block_at(0x24, {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	{
+		amp_set_page(0x1E);
+
+		amp_write_block_at(0x44, {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90
+		});
+	}
+
+	amp_set_book(0x8C);
+
+	{
+		amp_set_page(0x0E);
+
+		amp_write_block_at(0x5C, {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8
+		});
+
+		amp_write_block_at(0x7B, {
+			0xC1, 0xF8, 0x59, 0x7F, 0x63
+		});
+	}
+
+	{
+		amp_set_page(0x0F);
+
+		amp_write_block_at(0x08, {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7
+		});
+
+		amp_write_block_at(0x27, {
+			0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05,
+			0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF,
+			0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F,
+			0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04
+		});
+
+		amp_write_block_at(0x46, {
+			0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB,
+			0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8,
+			0xBB, 0x98, 0xC8
+		});
+	}
+
+	{
+		amp_set_page(0x10);
+
+		amp_write_block_at(0x08, {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x40, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_block_at(0x7D, {
+			0x11, 0xFF
+		});
+	}
+
+	{
+		amp_set_page(0x01);
+		amp_write_at(0x51, 0x05);
+	}
+
+	{
+		amp_set_page(0x02);
+		amp_write_at(0x19, 0xDF);
+	}
+
+	amp_set_book(0x8C);
+
+	{
+		amp_set_page(0x01);
+		amp_write_block_at(0x2C, {
+			0x00, 0x71, 0x94, 0x9A
+		});
+	}
+
+	{
+		amp_set_page(0x0A);
+
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x0B);
+
+		amp_write_block_at(0x08, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x37, 0xDF, 0xC0,
+			0x00, 0x37, 0xDF, 0xC0, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x28, {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x0E);
+
+		amp_write_block_at(0x5C, {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0x60, 0x3F, 0x2A,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5
+		});
+	}
+
+	{
+		amp_set_page(0x0F);
+
+		amp_write_block_at(0x5C, {
+			0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x1A, 0xB4, 0xF9
+		});
+	}
+
+	{
+		amp_set_page(0x07);
+
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x6C, {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0xAA);
+
+	{
+		amp_set_page(0x01);
+
+		amp_write_block_at(0x30, {
+			0x08, 0x10, 0x92, 0xFE, 0xF0, 0x84, 0x2F, 0xC0,
+			0x07, 0x6F, 0x67, 0x29, 0x0F, 0x7B, 0xD0, 0x40,
+			0xF8, 0x80, 0x05, 0xDA, 0x08, 0x18, 0xBA, 0xDB,
+			0xF0, 0xA9, 0xF7, 0x0B, 0x07, 0x44, 0x20
+		});
+
+		amp_write_block_at(0x4F, {
+			0x4E, 0x0F, 0x56, 0x08, 0xF5, 0xF8, 0xA3, 0x24,
+			0xD7, 0x08, 0x20, 0x24, 0xC9, 0xF1, 0x08, 0x6D,
+			0x45, 0x06, 0xE7, 0x92, 0x27, 0x0E, 0xF7, 0x92,
+			0xBB, 0xF8, 0xF8, 0x49, 0x10, 0x08, 0x13
+		});
+
+		amp_write_block_at(0x6E, {
+			0xEA, 0xAD, 0xF3, 0x14, 0xE9, 0xB1, 0x05, 0x4B,
+			0xD4, 0xF4, 0x0C, 0xEB, 0x16, 0x4F, 0xFA, 0xA0,
+			0x40, 0x5F
+		});
+	}
+
+	{
+		amp_set_page(0x02);
+
+		amp_write_block_at(0x08, {
+			0x08, 0x13, 0x8A, 0xBF, 0xF0, 0x78, 0x40, 0xD7,
+			0x07, 0x77, 0x45, 0xB3, 0x0F, 0x87, 0xBF, 0x29,
+			0xF8, 0x75, 0x2F, 0x8E, 0x08, 0x46, 0x76, 0x67,
+			0xF6, 0x0C, 0xF9, 0x7A, 0x03, 0x36, 0x96
+		});
+
+		amp_write_block_at(0x27, {
+			0xD5, 0x09, 0xF3, 0x06, 0x86, 0xFC, 0x82, 0xF2,
+			0xC4, 0x08, 0x0B, 0x02, 0xAF, 0xF0, 0xBC, 0xDB,
+			0x13, 0x07, 0x40, 0x84, 0x68, 0x0F, 0x43, 0x24,
+			0xED, 0xF8, 0xB4, 0x78, 0xEA, 0x08, 0x00
+		});
+
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x03);
+
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xB7, 0x9B, 0x16,
+			0xF0, 0x90, 0xC9, 0xD5, 0x07, 0xB7, 0x9B
+		});
+
+		amp_write_block_at(0x27, {
+			0x16, 0x0F, 0x6D, 0xB0, 0xA9, 0xF8, 0x8F, 0x44,
+			0x52, 0x07, 0xBB, 0x6D, 0x71, 0xF0, 0xCF, 0x04,
+			0xEA, 0x07, 0x7F, 0x86, 0x4C, 0x0F, 0x30, 0xFB,
+			0x16, 0xF8, 0xC5, 0x0C, 0x43, 0x08, 0x49
+		});
+
+		amp_write_block_at(0x46, {
+			0x93, 0xE5, 0xF0, 0x43, 0x4D, 0x1F, 0x07, 0x7D,
+			0x73, 0x57, 0x0F, 0xC0, 0x4F, 0x67, 0xF8, 0x3C,
+			0x95, 0x49, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x04);
+
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
+		});
+
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	{
+		amp_set_page(0x05);
+
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
+		});
+
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x07, 0xB7, 0x9B, 0x16, 0xF0, 0x90,
+			0xC9, 0xD5, 0x07, 0xB7, 0x9B, 0x16, 0x0F
+		});
+
+		amp_write_block_at(0x65, {
+			0x6D, 0xB0, 0xA9, 0xF8, 0x8F, 0x44, 0x52, 0x07,
+			0xBB, 0x6D, 0x71, 0xF0, 0xCF, 0x04, 0xEA, 0x07,
+			0x7F, 0x86, 0x4C, 0x0F, 0x30, 0xFB, 0x16, 0xF8,
+			0xC5, 0x0C, 0x43
+		});
+	}
+
+	{
+		amp_set_page(0x06);
+
+		amp_write_block_at(0x08, {
+			0x08, 0x49, 0x93, 0xE5, 0xF0, 0x43, 0x4D, 0x1F,
+			0x07, 0x7D, 0x73, 0x57, 0x0F, 0xC0, 0x4F, 0x67,
+			0xF8, 0x3C, 0x95, 0x49, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		});
+	}
+
+	{
+		amp_set_page(0x0E);
+
+		amp_write_block_at(0x6C, {
+			0x00, 0x99, 0xF7, 0x27, 0xFF, 0x09, 0x5A, 0xB9,
+			0x00, 0x66, 0xFF, 0x35, 0x0F, 0xB7, 0xB4, 0x87,
+			0xF8, 0x3D, 0xFA, 0x65
+		});
+	}
+
+	{
+		amp_set_page(0x0F);
+
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3D, 0x95,
+			0xFF, 0xFE, 0x7B, 0x29, 0xFF, 0xFF, 0x3D
+		});
+
+		amp_write_block_at(0x27, {
+			0x95, 0x0F, 0x62, 0x3F, 0x77, 0xF8, 0x9A, 0xB6,
+			0xDB, 0x07, 0xB1, 0xE2, 0x27, 0xF0, 0x9C, 0x3B,
+			0xB2, 0x07, 0xB1, 0xE2, 0x27, 0x0F, 0x62, 0x3F,
+			0x77, 0xF8, 0x9A, 0xB6, 0xDB, 0x00, 0x00
+		});
+
+		amp_write_block_at(0x46, {
+			0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A,
+			0x71, 0xC7
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x60, 0x00);
+		amp_write_at(0x63, 0x03);
+		amp_write_at(0x30, 0x00);
+		amp_write_at(0x4C, 0x30);
+		amp_write_at(0x03, 0x0B);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	mdelay(100);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x03);
+	}
+
+	return 0;
+}