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soc/intel: Add Meteor Lake IGD device id 0x7d45

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Add new IGD device.

Reference: EDS Vol 1 (640228)

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Ravi Sarawadi
2022-10-11 23:54:55 -07:00
committed by Subrata Banik
parent f2e2dc80fa
commit 33005df7bc
3 changed files with 6 additions and 3 deletions
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7
src/include/device/pci_ids.h
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@@ -4001,9 +4001,10 @@
#define PCI_DID_INTEL_ADL_N_GT2 0x46D1
#define PCI_DID_INTEL_ADL_N_GT3 0x46D2
#define PCI_DID_INTEL_MTL_M_GT2 0x7d40
#define PCI_DID_INTEL_MTL_P_GT2_1 0x7d50
#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d55
#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d60
#define PCI_DID_INTEL_MTL_P_GT2_1 0x7d45
#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50
#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55
#define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60
#define PCI_DID_INTEL_RPL_P_GT1 0xa720
#define PCI_DID_INTEL_RPL_P_GT2 0xa7a8
#define PCI_DID_INTEL_RPL_P_GT3 0xa7a0