This is a full rewrite of all the CS5530/CS5530A code. The previous code was
mostly undocumented, had a broken coding style, contained lots of dead code and had several other problems, e.g. it enabled write access to the ROM (why?), it unconditionally enabled primary/secondary IDE (which should have a config option) and that even _twice_ (which is um... wrong). The new code - has 'ide0_enable' and 'ide1_enable' config options (which actually work) to enable/disable the primary/secondary IDE interface in Config.lb. - Does _not_ enable write access to the ROM (or is there some good reason to do that? If so, it should at least have a config option). - Contains a bit more documentation. - Uses readable (and documented) #defines instead of hardcoded magic values. - aaand... it actually compiles ;-) Yep, that's right. The previous code wouldn't even build, as it hadn't been fully ported from v1 (still used v1 functions which are simply not available in v2). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -1,12 +1,31 @@
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#ifndef _SOUTHBRIDGE_AMD_CS5530
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#define _SOUTHBRIDGE_AMD_CS5530
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_AMD_CS5530_CHIP_H
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#define SOUTHBRIDGE_AMD_CS5530_CHIP_H
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extern struct chip_operations southbridge_amd_cs5530_ops;
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struct southbridge_amd_cs5530_config {
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/* PCI function enables so the pci scan bus finds the devices */
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int enable_ide;
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int enable_nvram;
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int ide0_enable:1;
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int ide1_enable:1;
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};
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#endif /* _SOUTHBRIDGE_AMD_CS5530 */
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#endif /* SOUTHBRIDGE_AMD_CS5530_CHIP_H */
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