sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names

Browse Source 
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
2010-12-26 05:16:47 +00:00
committed by Peter Stuge
parent 1c6d4e6055
commit 3344743215
3 changed files with 20 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/include/cpu/amd/gx2def.h
View File

@@ -15,10 +15,15 @@
#define CPU_REV_2_2 0x022
#define CPU_REV_3_0 0x030
/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
#define GLCP_CLK_DIS_DELAY 0x4c000008
#define GLCP_PMCLKDISABLE 0x4c000009
#define GLCP_CHIP_REVID 0x4c000017
/* GeodeLink Control Processor Registers, GLIU1, Port 3 ; MSR_GLCP = 4c00xxxx */
#define GLCP_CLK_DIS_DELAY (MSR_GLCP + 0x08)
#define GLCP_PMCLKDISABLE (MSR_GLCP + 0x09)
#define GLCP_DBGOUT (MSR_GLCP + 0x0C)
#define GLCP_PROCSTAT (MSR_GLCP + 0x0D)
#define GLCP_DBGCLKCTL (MSR_GLCP + 0x16)
#define GLCP_CHIP_REVID (MSR_GLCP + 0x17)
#define GLCP_TH_OD (MSR_GLCP + 0x1E)
#define GLCP_FIFOCTL (MSR_GLCP + 0x5E)
/* GLCP_SYS_RSTPLL, Upper 32 bits */
#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9