PCI subsystem: Refactor PCI bridge register control
Change-Id: I1766c92abe7a74326c49df74ba38930a502fcb5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8536 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
@ -81,6 +81,7 @@ struct bus {
|
||||
ROMSTAGE_CONST struct device * children; /* devices behind this bridge */
|
||||
ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */
|
||||
unsigned bridge_ctrl; /* Bridge control register */
|
||||
uint16_t bridge_cmd; /* Bridge command register */
|
||||
unsigned char link_num; /* The index of this link */
|
||||
uint16_t secondary; /* secondary bus number */
|
||||
uint16_t subordinate; /* max subordinate bus number */
|
||||
|
Reference in New Issue
Block a user