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soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names

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Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and
IA32_MC0_CTL is at 0x400.
So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at
0x400 by IA32_MC0_CTL.

Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Elyes HAOUAS
2018-09-26 18:21:48 +02:00
committed by Werner Zeh
parent 1e67f0773b
commit 339ae162b6
2 changed files with 8 additions and 7 deletions
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11
src/soc/intel/fsp_broadwell_de/cpu.c
View File

@ -128,11 +128,10 @@ void broadwell_de_init_cpus(struct device *dev)
static void configure_mca(void) static void configure_mca(void)
{ {
msr_t msr; msr_t msr;
const unsigned int mcg_cap_msr = 0x179;
int i; int i;
int num_banks; int num_banks;
msr = rdmsr(mcg_cap_msr); msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & 0xff; num_banks = msr.lo & 0xff;
/* TODO(adurbin): This should only be done on a cold boot. Also, some /* TODO(adurbin): This should only be done on a cold boot. Also, some
@ -140,14 +139,14 @@ static void configure_mca(void)
every bank. */ every bank. */
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
for (i = 0; i < num_banks; i++) { for (i = 0; i < num_banks; i++) {
wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr); wrmsr(IA32_MC0_STATUS + (i * 4), msr);
wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr); wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr);
wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr); wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr);
} }
msr.lo = msr.hi = 0xffffffff; msr.lo = msr.hi = 0xffffffff;
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC0_CTL + (i * 4), msr);
} }
static void broadwell_de_core_init(struct device *cpu) static void broadwell_de_core_init(struct device *cpu)

4
src/soc/intel/fsp_broadwell_de/include/soc/msr.h
View File

@ -21,9 +21,11 @@
#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_IA32_PLATFORM_ID 0x17
#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce #define MSR_PLATFORM_INFO 0xce
#define IA32_MCG_CAP 0x179
#define IA32_PERF_CTL 0x199 #define IA32_PERF_CTL 0x199
#define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TURBO_RATIO_LIMIT 0x1ad
#define MSR_IA32_MC0_STATUS 0x400 #define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401
#define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610 #define MSR_PKG_POWER_LIMIT 0x610
#define MSR_CONFIG_TDP_NOMINAL 0x648 #define MSR_CONFIG_TDP_NOMINAL 0x648