soc/intel/alderlake: Add support for I2C6 and I2C7

As per the EDS revision 1.3 add support for I2C6 and I2C7.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id918d55e48b91993af9de8381995917aef55edc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varshit B Pandya
2021-07-14 11:08:23 +05:30
committed by Felix Held
parent aefcab7ff6
commit 339f0e7e14
8 changed files with 31 additions and 1 deletions

View File

@@ -223,7 +223,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
config SOC_INTEL_I2C_DEV_MAX
int
default 6
default 8
config SOC_INTEL_UART_DEV_MAX
int