diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 5173b1cf03..042396ff42 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -72,6 +72,11 @@ enum soc_intel_alderlake_power_limits {
 	RPL_P_682_642_482_45W_CORE,
 	RPL_P_682_482_282_28W_CORE,
 	RPL_P_282_242_142_15W_CORE,
+	RPL_HX_8_16_55W_CORE,
+	RPL_HX_8_12_55W_CORE,
+	RPL_HX_8_8_55W_CORE,
+	RPL_HX_6_8_55W_CORE,
+	RPL_HX_6_4_55W_CORE,
 	ADL_POWER_LIMITS_COUNT
 };
 
@@ -86,6 +91,7 @@ enum soc_intel_alderlake_cpu_tdps {
 	TDP_35W = 35,
 	TDP_45W = 45,
 	TDP_46W = 46,
+	TDP_55W = 55,
 	TDP_58W = 58,
 	TDP_60W = 60,
 	TDP_65W = 65,
@@ -137,6 +143,11 @@ static const struct {
 	{ PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W },
 	{ PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W },
 	{ PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W },
+	{ PCI_DID_INTEL_RPL_HX_ID_1, RPL_HX_8_16_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_RPL_HX_ID_2, RPL_HX_8_12_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_RPL_HX_ID_3, RPL_HX_8_8_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_RPL_HX_ID_4, RPL_HX_6_8_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_RPL_HX_ID_5, RPL_HX_6_4_55W_CORE, TDP_55W },
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 2b9d3802a5..7a7855c877 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -90,6 +90,36 @@ chip soc/intel/alderlake
 		.tdp_pl4 = 114,
 	}"
 
+	register "power_limits_config[RPL_HX_8_16_55W_CORE]" = "{
+		.tdp_p1_override = 55,
+		.tdp_pl2_override = 130,
+		.tdp_pl4 = 200,
+	}"
+
+	register "power_limits_config[RPL_HX_8_12_55W_CORE]" = "{
+		.tdp_p1_override = 55,
+		.tdp_pl2_override = 130,
+		.tdp_pl4 = 200,
+	}"
+
+	register "power_limits_config[RPL_HX_8_8_55W_CORE]" = "{
+		.tdp_p1_override = 55,
+		.tdp_pl2_override = 130,
+		.tdp_pl4 = 200,
+	}"
+
+	register "power_limits_config[RPL_HX_6_8_55W_CORE]" = "{
+		.tdp_p1_override = 55,
+		.tdp_pl2_override = 130,
+		.tdp_pl4 = 200,
+	}"
+
+	register "power_limits_config[RPL_HX_6_4_55W_CORE]" = "{
+		.tdp_p1_override = 55,
+		.tdp_pl2_override = 130,
+		.tdp_pl4 = 200,
+	}"
+
 	# NOTE: if any variant wants to override this value, use the same format
 	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
 	# putting it under register "common_soc_config" in overridetree.cb file.
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index d78fc7ad5b..1ae95e60dc 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -301,6 +301,7 @@ uint8_t get_supported_lpm_mask(void)
 	case ADL_M: /* fallthrough */
 	case ADL_N:
 	case ADL_P:
+	case RPL_HX:
 	case RPL_P:
 		return LPM_S0i2_0 | LPM_S0i3_0;
 	case ADL_S:
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index bbcae49873..e6cab5129a 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -146,6 +146,11 @@ static const struct vr_lookup vr_config_ll[] = {
 	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
+	{ PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
 };
 
 static const struct vr_lookup vr_config_icc[] = {
@@ -184,6 +189,11 @@ static const struct vr_lookup vr_config_icc[] = {
 	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_ICC(90, 30) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_ICC(49, 30) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_ICC(37, 30) },
+	{ PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) },
+	{ PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) },
+	{ PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) },
+	{ PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
+	{ PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
 };
 
 static const struct vr_lookup vr_config_tdc_timewindow[] = {
@@ -222,6 +232,11 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
 	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
+	{ PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 };
 
 static const struct vr_lookup vr_config_tdc_currentlimit[] = {
@@ -260,6 +275,11 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
 	{ PCI_DID_INTEL_ADL_S_ID_11, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 46,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 39) },
 	{ PCI_DID_INTEL_ADL_S_ID_12, 35,  VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 30) },
+	{ PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
+	{ PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
+	{ PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
+	{ PCI_DID_INTEL_RPL_HX_ID_4, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
+	{ PCI_DID_INTEL_RPL_HX_ID_5, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },
 };
 
 static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg,