soc/intel/elkhartlake: Update FSP-M UPD related configs
Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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committed by
Patrick Georgi
parent
f303b4ffd9
commit
33f8fc698c
@@ -19,9 +19,10 @@
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#include <soc/usb.h>
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#include <stdint.h>
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#define MAX_HD_AUDIO_DMIC_LINKS 2
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#define MAX_HD_AUDIO_SNDW_LINKS 4
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#define MAX_HD_AUDIO_SSP_LINKS 6
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#define MAX_HD_AUDIO_SDI_LINKS 2
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#define MAX_HD_AUDIO_DMIC_LINKS 2
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#define MAX_HD_AUDIO_SNDW_LINKS 4
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#define MAX_HD_AUDIO_SSP_LINKS 6
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struct soc_intel_elkhartlake_config {
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@@ -63,16 +64,15 @@ struct soc_intel_elkhartlake_config {
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/* TCC activation offset */
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uint32_t tcc_offset;
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/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
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* When enabled memory will be training at two different frequencies.
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* 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
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* 4:FixedPoint3, 5:Enabled */
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/* System Agent dynamic frequency support.
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* When enabled memory will be trained at different frequencies.
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* 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2
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* (high), 4:Enabled */
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enum {
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SaGv_Disabled,
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SaGv_FixedPoint0,
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SaGv_FixedPoint1,
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SaGv_FixedPoint2,
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SaGv_FixedPoint3,
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SaGv_Enabled,
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} SaGv;
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@@ -96,12 +96,10 @@ struct soc_intel_elkhartlake_config {
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/* Audio related */
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uint8_t PchHdaDspEnable;
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uint8_t PchHdaAudioLinkHdaEnable;
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uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS];
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uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
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uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
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uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
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uint8_t PchHdaIDispLinkTmode;
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uint8_t PchHdaIDispLinkFrequency;
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uint8_t PchHdaIDispCodecDisconnect;
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/* PCIe Root Ports */
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uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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@@ -128,6 +126,10 @@ struct soc_intel_elkhartlake_config {
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/* Enable if SD Card Power Enable Signal is Active High */
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uint8_t SdCardPowerEnableActiveHigh;
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/* Gfx related */
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uint8_t Heci2Enable;
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uint8_t Heci3Enable;
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/* Gfx related */
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uint8_t SkipExtGfxScan;
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@@ -198,10 +200,6 @@ struct soc_intel_elkhartlake_config {
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/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
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bool CnviBtAudioOffload;
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/* Tcss */
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uint8_t TcssXhciEn;
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uint8_t TcssXdciEn;
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/*
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* Override GPIO PM configuration:
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* 0: Use FSP default GPIO PM program,
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