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soc/intel/apollolake: Move PMC BAR setup to bootblock

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Some features of PMC needs to be accessed before romstage. Hence,
move PMC BARs setup into bootblock.

BUG=chrome-os-partner:54149
BRANCH=none
TEST=none

Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15332
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Andrey Petrov
2016-06-22 18:58:14 -07:00
committed by Martin Roth
parent 0f593c22a8
commit 33fd66b463
2 changed files with 17 additions and 14 deletions
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17
src/soc/intel/apollolake/bootblock/bootblock.c
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@@ -134,8 +134,25 @@ static void enable_spibar(void)
spi_init();
}
static void enable_pmcbar(void)
{
device_t pmc = PMC_DEV;
/* Set PMC base addresses and enable decoding. */
pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */
pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
pci_write_config16(pmc, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
}
void bootblock_soc_early_init(void)
{
enable_pmcbar();
/* Prepare UART for serial console. */
if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
soc_console_uart_init();